Product Description CebaTech develops rapidly tunable intellectual property (IP) cores and PCI Express-enabled subsystem cards that accelerate complex software algorithms in silicon and systems. CebaTech’s offering addresses network, storage, storage area network (SAN), and communication applications. The company also performs turnkey chip and coprocessor subsystem design services.
CebaTech Solutions CebaTech developed its solutions with Synopsys using its C2RTM Compiler, an ESL high-level synthesis technology and flow. The innovative C2R solution rapidly synthesizes ANSI C to Verilog RTL, enabling CebaTech and Synopsys customers to realize complex software algorithms in a fraction of the time required by manual RTL development. Specific offerings include:
- CebaRIP Cores™ - Rapidly tunable IP cores for easy integration into ASIC and FPGA designs. These cores implement leading, standard data compression and encryption algorithms such as AES, DES, GZIP/GUNZIP, LZRW3, MD5, and SHA-1.
- CebaFlex Cards™ - Flexible, easy-to-integrate PCIe-enabled coprocessor boards that significantly accelerate complex protocols offloaded from the CPU.
- CebaSW Models™ - OSCI 2.0-compliant SystemC TLM models for virtual prototyping CebaTech’s IP cores and cards. Used for early pre-hardware integration, test, performance analysis, and for the development of low-end application code.
CebaTech’s advanced C2R ESL-based development flow integrates easily into the Synopsys Innovator virtual prototyping environment, and leverages industry-standard software development tools, such as GCC, GDB, and others.
Family | Protocols | I/F | Performance | Other |
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| Crypto | AES | FIFO | 64 Gbps | XTS, CBC, GCM, ECB | | Crypto | 3DES | FIFO | 64 Gbps | | | Crypto (DeDup) | Secure Hash Fast Digest | FIFO | Up to 20 Gbps | MD5, SHA1 AES-GMAC | | Compression | GZIP | FIFO | Up to 128 Gbps | Configurable History and Huffman | | Compression | GUNZIP | FIFO | Up to 64 Gbps | Configurable History and Huffman |
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Examples of CebaRIP Cores available with SystemC model support
Interoperability Description and Customer Benefit: CebaTech’s proven interoperability with the Synopsys Innovator virtual prototyping solution ensures that customers using its CebaRIP cores can quickly and seamlessly integrate and test their entire IP and system-on-chip before hardware implementation.
Customers using the CebaTech’s SystemC TLM models can significantly reduce design cycles and time-to-revenue. Specifically, they can:
- Deliver the “virtual” hardware to any number of software developers on day zero.
- Integrate and test driver software and application code before hardware availability.
- Validate the complete function and performance before hardware implementation.
- Communicate to CebaTech any additional custom feature requirements or performance optimizations before committing to hardware implementation.
Tell me more about CebaTech and Innovator and System Studio.
Flow Diagram 