Call for Papers

The SNUG India Call for Papers is closed.
Submit: Deadline to submit was March 12, 2010.
Review: Please review the submission and acceptance process.
Prepare: For the complete author submission timeline, please view the Author's Kit.

Share your experiences with Synopsys User's Group (SNUG); one of EDA's largest and most important events. For 20 years, SNUG has provided a unique forum for design professionals to learn about the latest in EDA technology, and how it is being used by many of the top companies to solve difficult design challenges and to improve design productivity, predictability, and profitability.

By following a simple outline and structure and with support from the SNUG technical committee, you can write and present an award winning paper at SNUG. Here are some of the elements of past top papers: Introduce the problem or challenge that you are addressing. Describe the approach that you took to analyze and address your challenge. Review lessons learned along the way (what was expected/unexpected, what went well/not so well). Why is your solution a good one? What can other designers take away and use from your paper? What are some ongoing areas of development or next steps that you (or an audience member) could pursue? Summarize your effort and results.

If you have used Synopsys technology to overcome difficult design issues, we want to hear from you! SNUG will cover exciting areas such as 40/45nm and 28/32nm design, as well as share insights and techniques to address challenges in low power, high-level or physical design methodology, RTL-to-GDSII design flows, FPGA design and verification, system simulation and verification and mixed-signal design.

Preliminary topics include (but are not limited to):

Physical Design:
Tapeout case studies at 32nm and below with advanced techniques ( Relative Placement, new CTS strategies, ,Signoff driven optimization)
High productivity flows ( early feasibility, DC-G/ICC flows, MCMM, multi-core )
Low Power Design Implementation using UPF
Hierarchical Design methodologies (ILMs, MIMs)
Leveraging Value Links (DC-G/ICC, ICC-ICV, ICC-PrimeRail, ICC-PrimeYield)
In-Design DRC – To cover applications throughout the flow, such as incremental DRC and Power Grid checking.
In-Design Metal Fill – To cover signoff-quality fill including productivity enhancing applications such as incremental fill and timing-aware fill.
In-Design Manufacturing Compliance – To cover Litho auto fix or other applications.
Signoff DRC/LVS – iDRC & iLVS

Verification:
Optimizing performance (VCS Multicore, general performance improvements, gate-level, constraint solver techniques, etc.)
Low power verification (VMM-Low Power, MVSIM, MVRC)
Advanced VMM (use of VMM applications, Verification IP with VMM, VMM 1.2)
Use of coverage technology (CCT, VMM Planner, Convergence with Magellan)
Transaction level verification (SystemC 2.0 modeling, transaction viewing with DVE)

Signoff:
Better, faster, cheaper: methods and capabilities for improving STA productivity
Deployment of Variation-Aware STA (SSTA and AOCV)
PTSI and CCS model deployment
PrimeTime ECO flow success stories
Power analysis and multi-voltage signoff flows
Parasitic extraction for fast, accurate signoff at advanced nodes
Transistor-level static timing analysis success stories

Synthesis:
Design Compiler Topographical
Design Compiler Graphical/Congestion removal
MCMM in DC
UPF/power flow
Multi-core in DC

Test:
DFTMAX/Test flow getting best coverage/compression
Test for SoCs integrating DFT and Testing across SoC
Diagnostics and yield
Timing aware – small delay defect, working with timing exceptions
On-chip clocking (using a lower cost tester)
Low pin count compression
Power-aware test
Multicore ATPG
Pattern validation

AMS:
Methodologies to handle reliability in designs 45nm and below
Analog/digital co-simulation methodologies
Extraction/simulation methodologies for effective Post Layout simulations
Methodologies for achieving high performance simulations

FPGA Design and Verification (Synplicity):
Optimizing FPGA turnaround time with SynplifyPremier
Partitioning large (>10M gates) SOCs with Certify; methodologies for high capacity ASIC prototyping in FPGA
Verifying complex SoCs using off-the-shelf FPGA rapid prototyping platforms
Implementing high speed serial interfaces with HAPS
Hardware/Software co-verification with CHIPit
Synplify-DSP and HAPS for DSP algorithm development and integration/test with larger SoC designs

IP:

Please contact the SNUG India Team with questions.