Session 1: Go Deep MVSIM
Pierre-Yves Alla [Synopsys France]
The goal of Low Power simulation is to verify the functionality of the design under a specific power network configuration or when the power supplies are changing. But it is also to validate the accuracy of your Power Intent file, by applying the same techniques used for years in HDL simulation. This tutorial will show you how MVSIM technology allows tackling those different situations, and ensure a high level of confidence in your complex Low Power design right from the RTL simulation. Tutorial  | Video not Available
Session 2: You Have the Power to TEST! (Part 1)
Power-Aware Test Solution
Nikolaus Mittermaier [Synopsys, Germany.]
This tutorial provides an overview and update on the latest Synopsys power-aware and pin limited testing features. It outlines how designers can generate patterns that are aligned with the functional power budget and reduce both dynamic and leakage power during scan testing. In addition to discussing the latest enhancements in the Synopsys Galaxy Test 2010.03 release, this session includes an introduction to using the latest pin-limited test architecture of DFTMAX™ compression. Finally YieldExplorer, one of the top 10 EDA tools of 2009, will be discussed with regards to its capabilities in analyzing design-based yield issues and accelerating root cause analysis.
Target audience: DFT, Test and Yield management engineers and managers that are involved in chip testing and yield improvements! Tutorial | Webinar 
Session 3: You Have the Power to Test! (Part 2)
Reducing the Cost of Pin-Limited Test Using DFTMAX Compression
David Johnson [Synopsys UK]
Designers are increasingly adopting design-for-test methodologies that limit the number of pins allocated for manufacturing test. In this tutorial, we will examine what is driving this trend and how you can use new capability in DFTMAX compression to reduce the cost of pin-limited test for your designs. Tutorial | Webinar
Session 4: Effective Post Layout Verification of AMS Designs at 28nm by means of StarRC Extracted Views
Hendrik Mau [GLOBALFOUNDRIES, Germany]
The design of analog mixed signal (AMS) circuits ,especially at 28nm, is a complex and ponderous process. Although thorough postlayout verification is required to ensure first-time-right silicon, it becomes easily prohibitive for larger AMS designs due to required simulation effort. A mixed configuration simulation strategy in a subdivided AMS postlayout verification flow is used by means of Extracted View Sets generated with StarRCXT. Strategies and methods for correct Extracted View generation will be presented and results from a real design implemented at 28nm are showing that post layout verification can be sped up, substantially improving the turn around time of the AMS design flow. Paper | Presentation | Webinar
Session 5: Scan Compression Without 'Scan Compression'
Richard Illman [Dialog Semiconductor, UK]
Scan compression tools have been available commercially for over 10 years and have been widely adopted. DFTMAX™ compression can achieve over 100x compression. However, small compression factors can be achieved using ”multi-mode” scan architectures. For small and medium size designs in the mixed-signal environment these provide a low cost alternative to full compression. This paper describes some examples and techniques for supporting them using DFTCompiler and Tetramax. Paper | Presentation | Webinar
Session 6: IC Compiler Feasibility, Planning and Implementation
Rainer Hadwiger [Synopsys, Germany]
Incorrect and incomplete design constraints are common in the early stages of the design cycle. This can lead to multiple iterations, long turnaround times, and even worse, poor design implementation that ultimately results in poor quality of results (QoR). This tutorial addresses feasibility during the pre-route stages of the design flow. It introduces an automated way to identify and analyze problems that impact timing, routability and congestion; a very fast optimization engine that efficiently deals with dirty data, and categorized timing reports that provide a detailed analysis of the violating endpoints that can be used to short-circuit the manual intervention process. Tutorial | Webinar
Session 7: Presentation on Efficient Analog IP Migration
Denis Goinard [Synopsys Inc]
The Synopsys MSIP group is leader in the design and development of Analog and Mixed Signal IP, with over 200 engineers worldwide. They are now exclusively using Synopsys’ Custom Designer layout and full custom solution. The session will be a presentation of how the flexibility and programmability of Custom Designer was used by the Synopsys MSIP group to create a migration flow for efficiently up-scaling 65nm analog IP to 130nm that is DRC & LVS clean and fully functional. Tutorial | Video not Available
Session 8: ICC-IC Validator and ICC-PrimeRail New ‘In-Design’ Features
Salvatore D’Argenio [STMicroelectronics, France]
Sequential flows often lead to unrepairable issues. In-design reliability analysis and physical verification not only save precious time by avoiding useless translations of data back and forth; they also allow us to catch and fix the problems on the go, preventing costly iterations between implementation and sign-off. Paper | Presentation | Webinar
Session 09: Generating Low-Power ATPG Patterns using a Shift Power Effort
Pascal Blanc [ST-Ericsson, France]
In the past, TetraMAX provided a power-aware test pattern generation that performed low-power fill during shift cycles. However, this adjacent fill algorithm was not efficient enough for designs that embed scan compression logic. Knowing that, Synopsys developed a new ATPG low-power algorithm that gives the capability to control the switching activity during scan shift. The new algorithm is ATPG based and doesn’t require any design change, allowing us to use the new patterns on existing designs to address power issues when they appear on the tester. This technical paper presents our experimental work and the associated conclusions based on the simulation and silicon results on two different designs. Paper | Presentation | Webinar
Session 10: Experiences with ICC Black Box Flow
Herbert Preuthen [LSI, Germany]
This paper describes the experience made while using the black-box flow in ICC for early floorplanning analysis and timing checks in a 65nm ASIC with large busses. It explains the creation of black-box layout views and QTMs when the design still is in “dirty-netlist” stage and where only a small portion of the RTL is coded. The flow makes it possible to give early feedback on top level timing bottlenecks, timing budgets, congestion and can guide the RTL design into an implementation friendly style. This approach saves development time and, for the first time, supports a real RTL- backend co-design. Paper | Presentation | Webinar
Session 11: Scan Compression with Limited Pin Access
Chris Dodd [Wolfson Microelectronics plc, UK]
To keep within the limitations of the test equipment, DFTMAX™ Compression has been an essential tool for Wolfson to enable high quality testing of silicon. The digital content of Wolfson’s devices has been steadily increasing, along with the reduction of digital pins available on the package. This presentation covers how the latest Pin Limited Testing enhancements have been deployed successfully on Wolfson’s latest devices. Presentation | Webinar
Session 12: Galaxy Constraints Analyzer: Constraints Debugging Made Easy
Emmanuel Pluchart [Synopsys, France]
Today’s designs are getting larger and more complex: it is not unusual to get hundreds of clocks, power management, multiple modes, in-house or 3rd party IPs with their own set of timing constraints that need to be integrated at the top level. In addition, designs are being developed over geographically dispersed teams. With this increased complexity together with tighter schedules and shorter deadlines, finalizing the design timing constraints is becoming extremely challenging. Tutorial | Webinar
Session 13: Energy Efficient Processor Implementation with Synopsys’ Eclypse Low Power Solution
Alan Gibbons [Synopsys Ltd.]
Delivering the energy efficient performance demanded by today's mobile devices is the focus for many design teams and requires the integration of high performance techniques together with intelligent power management in a streamlined methodology. Concurrent optimization of power and performance is a primary benefit of Synopsys’ Eclypse Low Power Solution and this tutorial will discuss the aspects of the Eclypse solution that enable designers to meet these aggressive power and performance targets. This tutorial provides a technical case study of a 32nm Eclypse based implementation of an ARM Cortex-A5 multi-processor with IEEE-1801 UPF based power intent.
Target audience: SoC engineers working on low power implementation with specific relevance to those working on synthesizable ARM processors. Tutorial | Webinar
Session 14: Clock Tree implementation techniques - a comparative analysis
Ina Shtarkberg [Intel Corporation]
One of the biggest challenges in chip and block design is implementing the clock tree. Clock tree implementation has a vast impact on design timing closure, design size and above all the dynamic and leakage power the design will consume. In recent years, as more devices are targeted into mobile equipment, there is greater thought invest on minimizing the power consumption. This paper will demonstrate two techniques of clock tree implementation and will present comparative analysis data on various metrics resulting from each one. The first one is traditional cluster based clock tree which is very common in ASIC flows (CTS), the other is a unique technique used in various high frequency designs which is based on non-uniform fishbone mesh. Paper | Presentation | Webinar
Session 15: Simulation Acceleration using Multicore Systems
Itai Yarom,[Intel Corporation]
The functional verification effort is one of the main efforts in chip design flows. In this paper we present how to take advantage of multicore systems in order to accelerate the simulation performance. We take advantage of the multicore support provided by the leading hardware simulators and we enhanced in two ways. First, we introduce an algorithm for automatically partitioning the design for multicore simulation. Second, we present an approach to use the graphical processing unit (GPU) in order to increase the simulation acceleration further (around x100 faster). Paper | Presentation | Webinar |