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SNUG Awards |
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1st Place - Best Paper
Germany | Experiences with ICC Black Box Flow
Author(s): Farid Labib, Herbert Preuthen [LSI, Corp.]
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| | Singapore | User Paper 8: Making DFM Sense In Your Design
Author(s):
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| | San Jose | Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design
Author(s): Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee, Bruce Doyle [Advanced Micro Devices, Inc.], Zhi-Yuan Wu [GLOBALFOUNDRIES], Reza Moallemi [Synopsys, Inc.]
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| | UK | Scan Compression Without "Scan Compression"
Author(s): Richard Illman , Hans-Martin von Staudt [Dialog Semiconductor Ltd.]
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| India
| Finding Power-up Issues in Memories using ESP-CV
Author(s): Premkumar, Sanjeev Suman [Texas Instruments], Rakesh Shenoy [Synopsys]
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| | | Efficient Prototyping of Multi-Million Gate SoCs using Accelerated Synthesis Feature of Synplify Premier
Author(s): Sabyasachi Dey, Amit Siroya [Qualcomm]
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| | | Physical Implementation Challenges for a Very Large, Channel-Dominated, Multi-Clock Design in 45nm
Author(s): Namit Varma, Madhusudan Rajagopal, Veena Radhakrishnan [Achronix]
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| | | On Analysis & Development of Sign-Off Quality Clock Gating Effectiveness Metrics
Author(s): Jairam Sukumar, Udayakumar H, Rajagopal K A [Texas Instruments], Maria Tovey [Synopsys]
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| | | Achieving massive multi-site testing without compromising on the test quality - Is Serializer the solution?
Author(s): Malav Shah, Claus kuntzsch, Nikolaus Mittermaier [Texas Instruments]
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| | | Verification of Mixed-Signal Designs using System-Verilog Assertions in Co-simulation
Author(s): Somasunder Kattepura Sreenath, Sandeep Tare [Texas Instruments] | | |
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| | | | | | Technical Committee Award Honorable Mention
UK | Scan Compression Without "Scan Compression"
Author(s): Richard Illman , Hans-Martin von Staudt [Dialog Semiconductor Ltd.]
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| | Germany | Massive Test Cost Reduction by Advanced SCAN Testing
Author(s): Claus Kuntzsch, Malav Shah [Texas Instruments] Nikolaus Mittermaier [Synopsys, GmbH]
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| | San Jose | Reusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem
Author(s): Krishna Vittala [Microchip Technology Inc.]
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| | | Interoperable Testbenches using VMM TLM
Author(s): Asif Jafri [Verilab Inc.], Nasib Naser [Synopsys, Inc.]
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| | Taiwan | Low Power Design & Verification for PACDSP
Author(s): C. Y. Liao, H. C. Hsieh, Chen-An Chen, Po-Han Huang, Shing-Wu Tung [ITRI]
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| | | Methodology of Executable Verification Plan
Author(s): Shang-Wei Tu, Tom Lin [Sunplus] | | |
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