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Conference at a Glance |
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SNUG Silicon Valley | March 26-28, 2012
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Monday, March 26, 2012
| Time | Description | | 7:30-9:00 | Registration | | 9:00-10:30 | WELCOME: John Busco - SNUG Silicon Valley Technical Chair, NVIDIA
KEYNOTE ADDRESS: Dr. Aart de Geus - CEO & Chairman of the Board, Synopsys, Inc. | | 10:30-11:00 | Break | | | IC Design - Implementation A | IC Design -
Implementation B | IC Verification | AMS Verification | FPGA | IC Design -
Signoff | | | 11:00-12:30 | MA1 Tutorial
Galaxy
RTL: Design Compiler
Family Update
Synopsys, Inc. | MA2 Tutorial:
IC Compiler
Custom
Co-Design
Synopsys, Inc. | MA3 User:
UVM Factories & USB 3.0
Verification
The OVM/UVM Factory & Factory Overrides -
How They Work -
Why They Are Important
Sunburst Design
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Integrating DesignWare USB3.0 Device Controller In a UVM-Based Testbench
Paradigm Works | MA4 User:
Advanced Analysis with HSPICE & CustomSim-VCS
Statistical Margin Sensitivity to RNG option for Monte Carlo Simulations with HSPICE
ARM
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UVM based Random Verification in Analog and Mixed Signal Designs for Faster Coverage Closure
AMD | MA5 Tutorial:
Considerations in Using FPGAs as System Elements
Synopsys, Inc. | MA6 User & Tutorial: Signoff-Driven Design
Closure
PrimeTime DMSA ECO Fix: a Case Study
Cypress Semiconductor
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ECO Timing Closure: Fast and Flexible Multi-Scenario DRC Fixing
Synopsys, Inc. | | | 12:30-1:45 | Lunch | |
| | IC Design - Implementation A | IC Design -
Implementation B | IC Verification | AMS Verification | FPGA | IC Design -
Signoff | IC Design - Custom Design | | 1:45-3:15 | MB1 User: Design Correlation
Improving
Virtual Route Correlation
on Advanced Process
Nodes
Intel
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The Impact
of Correlation
on Design Quality, Design Closure Loops, & Design Turn Around Time
Intel
| MB2 Tutorial:
Accelerating Manufacturing
Closure at
28nm and
below with
IC Validator
and In-Design Technology
Synopsys, Inc. | MB3 User:
Minimizing
RTL-to-Netlist Simulations Mismatches
VCS X-Prop:
An Alternative
to Gate Level Simulation
Cisco Systems Inc.
------Simulation/
Synthesis Mismatches Again?
Microchip Technology | MB4 User & Tutorial: Testability for Custom Logic & 28nm Cell Characterization
Challenges
Enabling DFT Logic & Timing Verification in Mixed-Signal Designs with XA & VCS Cosim
Rambus
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Standard Cell Library
Characterization
Flow using Liberty-NCX & HSPICE
Synopsys, Inc. | MB5 Tutorial:
Design Reliability Challenges for 28nm and Beyond
Synopsys, Inc. | MB6 Vision: Signoff for Increasingly Complex
Designs
Synopsys, Inc.
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Q&A Panel
Synopsys, Inc. | MB7 Workshop: Custom Designer
Synopsys, Inc. | | 3:15-3:45 | Break | | | IC Design - Implementation A | IC Design -
Implementation B | IC Verification | AMS Verification | FPGA | IC Design -
Signoff | System Level Design | | 3:45-5:15 | MC1 Tutorial:
Design Correlation & Flipchip Package Design
Intelligent & Automated Layer-Aware Pre-Route Optimization for Improved Post-Route Correlation for Advanced Technology Nodes
Synopsys, Inc.
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A Chip-Package Design Flow Using Zuken and Synopsys Tools
Zuken, Synopsys, Inc. | MC2 User &
Tutorial:
IC Validator
Enabling DRC+ Pattern-based
Physical
Verification with
IC Compiler &
IC Validator
GLOBALFOUNDRIES
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Optimizing Design Fill at 28nm and below using
In-Design Physical Verification with IC Validator
AMD | MC3 User: Enhancing Self-Checking Testbenches
Snooping to Enhance Verification in a VMM Environment
LSI Corp.
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A Unified Self-Check Infrastructure
Charles Stark
Draper Labs | MC4 Tutorial:
How to Get the Most from Your Circuit Simulation
Synopsys, Inc. | MC5 User: FPGA Design
Design & FPGA Implementation of FIR Filters using Microprogram Control Unit
King
Abdulaziz City for Science & Technology | MC6 Tutorial: Static Timing Technology
Performance
& Productivity Improvements in PrimeTime 2011 Release
Synopsys, Inc.
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Galaxy Constraints Analyzer: Comparing Multiple SDC Constraints Files
Synopsys, Inc. | MC7 User & Tutorial:
UVM for ESL and HLS for Multi-Rate Comm. Designs
Does UVM Make Sense for ESL?
Doulos Inc.
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Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design
Synopsys, Inc. | | 4:00-8:00 | Designer Community Expo |
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Tuesday, March 27, 2012
| Time | Description | | 7:30-9:00 | Registration | | 9:00-10:00 | Keynote Address: John Cornish, Executive VP - ARM | | 10:00-10:30 | Break |  | IC Design - Implementation A | IC Design - Implementation B | IC Verification | | FPGA | IC Design - Signoff | System-Level Design | | 10:30-12:00 | TA1 User:
Low Power Design
Power Gating using UPF,
DC and ICC
for a PCIE Design
AMD
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Energy Harvesting
with an ARM Cortex-M0:
A Novel Application
of UPF with Synopsys™ Galaxy Platform to Implement Sub-Clock Power Gating
University of Southampton; ARM Ltd | TA2 Vision & Tutorial: Advanced Design Integration – 2.5DIC and 3DIC
A Silicon Interposer-Based 2.5D-IC Design Flow - Going 3D by Evolution Rather Than by Revolution
Synopsys, Inc.
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Xilinx FPGAs with SSI Technology – Concept to Silicon development overview
Xilinx | TA3 User: UVM RAL & Solution for X Propagation Easier RAL: All You Need to Know About the UVM Register Abstraction Layer
Doulos
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Enhanced simulation support for non-deterministic values
Freescale | | TA5 User & Tutorial: FPGA Prototyping
Slow Dancing with Memories - Sometimes it's Harder to Go Slow
SanDisk
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Determining Optimal FPGA System Connectivity
Synopsys, Inc. | TA6 User: MultiVoltage and Low Power Analysis Technologies
28nm ETM Generation with Multi-voltage Domain(UPF compliant) and Embedded IO
LSI
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Early Leakage Power Estimation for Use Cases Across PVT
Broadcom | TA7 User:
Designing Custom Processors as an Alternative to Fixed HW Blocks
Programmable Accelerator for a Mobile SoC
Audience
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Deploying Processor Designer for a Custom Super Scalar Processor for Software Defined Radio
Fujitsu | | 12:00-1:15 | Lunch | | IC Design - Implementation A | IC Design - Implementation B | IC Verification | | FPGA | IC Design - Signoff | System-Level Design | | 1:15-2:45 | TB1 User & Tutorial: Automated Design Planning & Design Closure
Hippo Lake:
A Case Study of Automated Design Planning in High Speed Designs
Intel Corp.
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Faster Top Level Closure With Transparent Interface Optimization (TIO) Synopsys, Inc. | TB2 Vision:
Designing 100 Billion Transistor Chips
Synopsys, Inc. | TB3 User:
Simultaneous C/Assembly/RTL Debug with DVE & SimpleTest Writer Interface with SystemVerilog Gate & RTL Level Simulation with Software Debug Capability - An Integrated Signal and C-code Debugger in DVE
Broadcom Corp.
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Mechanism to Allow Easy Writing of Test Cases in a SystemVerilog Verification Environment, Then Auto-Expand Coverage of the Test Case
Verifysys | | TB5 User & Tutorial:
FPGA
Prototyping
Functional Coverage for FPGA Prototypers Opens a new Paradigm
Intel
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Effective Strategies for Bringing Up and Debugging an FPGA-Based Prototype
Synopsys, Inc. | TB6 Tutorials:
Parasitic Extraction for Emerging Technologies
Dealing with Metal Fill in 28nm ECO Extraction Flow
Synopsys, Inc.
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Double-Patterning Aware Extraction & Timing Signoff at 20nm
Synopsys, Inc.
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How do FinFETs Impact Parasitic Modeling & Extraction?
Synopsys, Inc. | TB7 User:
Early SoC Architecture Performance Analysis
System on Chip (SoC) Architecture/
Performance Modeling using SystemC/TLM 2.0, a Case Study using Platform Architect
LSI
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Architecture Analysis of a Multi-Mode Base-Station Huawei | | 2:45-3:15 | Break | | IC Design - Implementation A | IC Design - Implementation B | IC Verification | IC Design - Test | FPGA | IC Design - Signoff | System-Level Design | | 3:15-5:15 | TC1 Tutorial:
Techniques for High Performance Cores using Synopsys Galaxy Platform - ARM® Cortex™-A15 Case Study
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Best Practices for High Performance Processor Core Implementation | TC2 User Session: Clock Tree Design
Multi-Source CTS in ICC
AMD
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Gater Expansion with a Fixed Number of Levels to Minimize Skew
AMD | TC3 Tutorial:
AXI 4 VIP and Low-Power Simulation Debug
Achieving Rapid Verification Convergance with AMBA AXI4 VIP
Synopsys, Inc.
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Debugging Low-Power Simulations
Synopsys, Inc. | TC4 Panel:
Testing High-Frequency and Low-Power Designs: Do the Standard Rules Apply?
Oracle, Synopsys, Inc. | TC5 User &
Tutorial:
FPGA Design Unleashing the Power of the Command-Line Interface
Centellax
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Solving P&R Challenges on High Density Xilinx FPGAs
Xilinx | TC6 Tutorial: Signoff using Formal Equivalence Checking
Formality Low Power Equivalence Checking with UPF
Synopsys, Inc.
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ESP Memory Redundancy Verification
Synopsys, Inc. | TC7
Tutorial:
Enabling
Early
Software
Development for
ARM-Based Designs
Developing Software for ARM
big.LITTLE Based
Designs Running Android
ARM;
Synopsys, Inc.
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SoC FPGA Virtual Target: An Application
of Virtual Prototyping
Synopsys, Inc. | | 4:30-7:00 | SNUG Pub |
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Wednesday, March 28, 2012
| Time | Description | | 7:30-9:00 | Registration | | 9:00-10:00 | | | 10:00-10:30 | Break | | | IC Design -
Implementation A | IC Design - Test | IC Verification | Compute & Design
Infrastructure | IPSummit at SNUG | | 10:30-12:00 | WA1 User:
Design Planning
Powerful Things
you Can Do with
Template-Based
Power
Network
Synthesis
Combined
with Basic Polygon
Operations in
IC Compiler
Cypress
Semiconductor
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Developing &
Implementing
a Flip Chip
Interface using
IC Compiler
Samsung | WA2 User:
Optimizing
Test Time
with SerDes
& Mfg. Data Analysis with
Yield Explorer
Commonality Analysis with
Yeald Explorer
NVIDIA
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Optimizing Test
Times using Deserializer/
Serializer Scan Architecture
NVIDIA | WA3 Tutorial:
VCS Technology
& Testbench Methodology
for Achieving
Higher Video throughput
Synopsys, Inc. | WA4 Tutorial: Compute Farm
Infra. for EDA
Optimizing
Scale Out for Synopsys
EDA Tools
using a Common
Distributed Processing Framework
Synopsys, Inc.
------Rightsizing EDA Infrastructure
& Impact of Low Power
Processors on EDA
Synopsys, Inc. | WA5 Tutorial:
Best Practices
to Implement Memories &
Libraries to
Deliver
Superior PPA & Embedded Test & Repair
Synopsys,
Inc. | WA6 Tutorial
Designing to
the New PCI
Express 3.0
Equalization
Requirement
Synopsys, Inc. | WA7 Tutorial
Tag – You’re
it! Passive,
Unclonable
RFID Tags
Made Possible
Verayo | | 12:00-1:15 | Lunch | | | IC Design -
Implementation A | IC Design - Test | IC Verification | Compute & Design
Infrastructure | IPSummit at SNUG | | 1:15-2:45 | WB1 Tutorial:
IC Compiler:
Achieving Design
Success at 20nm
Synopsys, Inc. | WB2 User:
Power Efficient Clocking
for Test & Custom
Scan Chain
Stitching
with DFTC
Power-Efficient Functional & Scan Clocking for High Performance Cores
AMD
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Scan Stitching Separate Groups of Mux-D or LSSD
Flops
AMD | WB3 Tutorial:
Getting X Propagation under
Control
Synopsys, Inc. | WB4 Tutorial: Compute Farm Resource
Usage &
Optimization
Business Rules Monitoring – Automated
Resource Policy
Implementatin
Altera;
Synopsys, Inc.
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Leveraging
Adaptive Resource
Optimization with Lynx
Synopsys, Inc. | WB5 Tutorial:
Meeting Quality
of Service
Requirement
with DDR
Memory
Controllers
Synopsys, Inc. | WB6 Tutorial:
Create a
Complete
Audio IP
Subsystem
for Your
SoC in
Minutes
Synopsys, Inc. | WB7 Tutorial:
Getting the
Most from
Synthesis
to Improve
Your
Datapath
QoR
Synopsys, Inc. | | 2:45-3:30 | Break and Awards Presentations | | | IC Design -
Implementation A | IC Design - Test | IC Verification | Compute & Design
Infrastructure | IPSummit at SNUG | | 3:30-5:00 | WC1 Tutorial:
Advanced
Multichip
Designe
Synopsys’
Silicon
Interposer
(2.5D IC)
Implementation Solution
Synopsys, Inc.
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Creating
Multi-IO
Ring Die using
IC Compiler
Synopsys, Inc. | WC2 Tutorial:
Test Updates,
Yield Improvement, and the Importance
of Standards
Synopsys, Inc. | WC3 Tutorial:
VCS Technologies for Efficient Development and Debug
of UVM Testbenches
Synopsys, Inc. | WC4 Tutorial:
Management
of High-Performance Compute Resources
Understand the Impact of NFS Overhead
Synopsys, Inc.
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HPC for Silicon Design Inside Intel
Intel | WC5 Tutorial:
USB 3.0: Ready,
Set, Integrate!
Synopsys, Inc. | WC6 Tutorial:
Future
Mobile Interfaces
& Integration of MIPI DigRF in Mobile
Baseband Processors
MIPI | WC7 Tutorial:
The Role of
IP in More
Moore &
More than
Moore
Synopsys, Inc. |
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