This past March Sun Microsystems™ published the entire RTL for its advanced UltraSPARC® T1 processor along with the corresponding verification test suite, simulation models, and development tools on the public web site, www.opensparc.net. This contribution represents over 14 million lines of code placed by Sun into the public domain. The significance of this event is that it allows universities and research institutions the ability to use this technology free of charge under a GNU General Public License (GPL).

The open source version of Sun's UltraSPARC T1 design is called "OpenSPARC™ T1". OpenSPARC T1 represents Sun's latest 8-core, 32-thread, 64-bit multi-threading (CMT) processor giving universities the opportunity to use a state-of-the-art microprocessor design in new research projects or in coursework and laboratory studies development.

One example of the use of the OpenSPARC T1 RTL was presented at the Design Automation Conference 2006. The complete RTL (Verilog) design of the OpenSPARC T1 was verified using Synopsys®' VCS running with Solaris 10 on Sun's latest two-socket AMD Opteron™- based Ultra 40 workstation. This demonstration represented the clean simulation of approximately one-half million lines of RTL code in less than thirty minutes utilizing this environment.

Sun's intent behind the OpenSPARC effort is to create a public ecosystem around SPARC technology that allows companies, research institutions, and universities the ability to freely create innovative new multi-core designs and uses from this technology. This is the first time that such an advanced hardware design has been released under the GNU GPL and reflects Sun’s continued commitment to the open source development model.

Complementing the publication of the Open SPARC T1 Verilog design are complete verifications suites, simulation models, an instruction set architecture specification, and Solaris 10 OS simulation images. It is also Sun's intent to release a working single-core version of the OpenSPARC T1 in FPGA specifically targeted for academic use in microprocessor research projects. This FPGA synthesis will also be accessible and downloadable from the OpenSPARC web site following successful completion and testing.

To start innovating today using OpenSPARC or for more information visit the web-site at www.opensparc.net