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Seminar Series 2010
Attend a Synopsys technical seminar near you
Webinars
View our online webinars and learn from technology experts on a variety of topics.
SNUG Conferences
Forum for Synopsys users to exchange, discuss and explore ideas
Workshop Series 2010
Hands-on learning from Synopsys experts
News
Synopsys First to Deliver High-Performance Audio IP in 40-nm and 55-nm Process Technologies
Synopsys' Design Compiler Graphical Shortens Design Schedule at Oticon
Foveon Switches to Galaxy Custom Designer Solution to Accelerate Time-to-Tapeout
Synopsys and Virage Logic Announce Expiration of Hart-Scott-Rodino Waiting Period for Proposed Acquisition
SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100 Percent Silicon Success
Media Advisory/Alert: Synopsys Demonstrates Interoperability of DesignWare IP for PCI Express 3.0 at PCI-SIG Developers Conference
Synopsys Honors IEEE-ISTO with Tenth Annual Tenzing Norgay Interoperability Achievement Award
Synopsys CFO Brian Beattie to Speak at NASDAQ OMX 24th Investor Program
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Blogs
Low Power Blog: Magic Blue Smoke
A View from the Top: A System-Level Blog
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
On Verification: A Software-to-Silicon Verification Blog
Standards Blog: The Standards Game
USB IP Blog: To USB or Not to USB
The Eyes Have it: An IP Blog
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Webinars
Manufacturing-Aware Routing at 32/28nm
Power Analysis using PrimeTime PX
Simulation of Power Devices with TCAD
The Next Generation of Ethernet
Realizing 32nm Large Capacity Designs
StarRC Custom Rapid3D Technology
Utilizing Design Compiler 2010 Technologies
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Events
ASQED (Asia Symposium on Quality Electronic Design) 2010
SNUG China
SNUG Singapore
SNUG Taiwan
SPIE Photomask Technology
SNUG Boston
SNUG Ottawa
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A
AMBA
AMS Co-Sim
Audio IP
C
Cadabra
CATS
Certify
CHIPit.com
Circuit Check
CoMET
CoMET/METeor Models
Confirma
coreAssembler
coreBuilder
coreConsultant
Custom Designer LE
Custom Designer SDL
Custom Designer SE
Custom WaveView
CustomExplorer
CustomSim
D
Data Converters
Datapath
DC Ultra
DDR
Design Compiler Graphical
Design Services
DesignWare
DesignWare System-Level Library
Device Controller
DFTMAX
DSP model libraries
E
Eclypse Low Power Solution
ESP-CV
Ethernet
F
Fammos TX
Formality
FPGA Design
G
Galaxy Constraint Analyzer
H
HAPS
HDMI IP
Hercules
HSIM
HSIM Plus
HSPICE
I
I2C
IC Compiler
IC Validator
IC Workbench Plus
Identify
Identify Pro
Implementation
Innovator
Interconnect Simulation
IP
J
JPEG
L
Leda
Liberty NCX
Lynx Design System
M
Magellan
Manufacturing
Memory Models
M
Microcontrollers
Mobile Storage
MVRC Multi-voltage Rule Checker
MVSIM
N
NanoSim
NanoTime
O
OCP
Odyssey
P
PCI Express
PCI/PCI-X
Pioneer-NTB with Vera
Platform Architect
Platform Architect Models
Power Compiler
PrimeRail
PrimeTime
PrimeYield
Process Simulation
Processor Designer
Proteus
Proteus MetroKit
PSM-Check and Create
R
Raphael
S
Saber
Saber Harness
Saber Simulator
SATA
Seismos CX
Seismos LX
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Topography
Serial I/O
Signoff
SPW
Star IP
StarRC
Synplify DSP
Synplify Premier
Synplify Pro
System Level Library
System Studio
T
Taurus-Medici
Taurus-TSuprem4
TCAD
TetraMAX ATPG
Touch Screen Controllers
U
USB
V
VCS
VCS Verification Library
Verification
Verification IP
Video Analog Front Ends
Virtual Prototyping
W
Wireless USB
X
XA Technology
XAUI
Y
Yield Explorer
Z
Zroute
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