The DesignWare® DDRn Memory Interface is a family of complete system-level IP solutions for SoCs requiring an interface to the broad range of high-performance DDR3, DDR2, DDR, Mobile DDR, and LPDDR2 SDRAM memory subsystems. Optimized for improved data bandwidth, low power and enhanced signaling features, the complete DesignWare DDRn IP solutions include a choice of scalable digital memory and protocol controllers, an integrated hard macro PHY delivering memory system performance of up to 2133 Mbps per bit, and verification IP. Support for Mobile DDR SDRAMs is included in most DDR2/3-Lite products. All Synopsys DDRn PHYs include a DFI 2.1 compliant interface to the controller.

Synopsys offers two choices in regard to the DDR digital controller IP. The Memory Controller family represents full-featured, general-purpose memory controllers which convert host port memory requests into DDR transactions and include support for up to 32 host ports, flexible port arbitration, and advanced command reordering/scheduling to optimize DDR data bus utilization. The Protocol Controller family offer a low-latency, high performance single port controller which converts host port memory requests into DDR transactions and is ideally suited to accommodate custom-designed memory management units. The Universal DDR Protocol and Memory Controllers feature a DFI 2.1-compliant interface to the DDR PHY.