Synopsys DesignWare PCI Express 3.0/2.0/1.1 (Gen3/Gen2/Gen1) IP Cores for SoC Design and Verification

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PCI Express

DesignWare IP Solutions for PCI Express

Overview

Synopsys offers a complete, silicon-proven DesignWare® IP for PCI Express® solution consisting of a suite of digital cores, PHY IP and verification IP(VIP), all of which are compliant to the PCI Express 3.0, 2.0 and 1.1 and PIPE specifications. As the leading supplier of PCI Express IP, Synopsys is focused on delivering high quality IP. The DesignWare IP for PCI Express has gone through extensive third party interoperability testing with products shipping in volume production. The strict quality measures combined with an expert technical support team enables designers to accelerate time-to-market and reduce integration risk for next generation desktop, mobile, consumer and communication system-on-chips.
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Complete Solution Datasheet for PCI Express

DesignWare IP for PCI Express 2.0 Complete Solution Demo

Products
Highlights

Endpoint
Configurable PCIe 3.0, 2.0 and 1.1 IP for Endpoint applications more

Implements the port logic required for a PCIe Endpoint and it is compliant with the PCI Express 3.0, 2.0 and 1.1 and PCI-SIG SR-IOV specifications.
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Root Port
Configurable PCIe 3.0, 2.0 and 1.1 IP for Root Complex applications more

Implements the port logic required for a PCIe Root Complex and it is compliant with the PCI Express 3.0, 2.0 and 1.1 specifications
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Dual Mode
Configurable PCIe 3.0, 2.0 and 1.1 IP for RC or EP applications more

Implements the port logic required for both a PCIe Root Complex and Endpoint and it is compliant with the PCIe 3.0, 2.0 and 1.1 and PCI-SIG SR-IOV specifications.
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Switch Port
Configurable PCIe 3.0, 2.0 and 1.1 IP for Switch applications more

Implements the upstream or downstream port logic required for a PCIe Switch or Bridge and it is compliant with the PCI Express 3.0, 2.0 and 1.1 specifications.
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PCI Express to AHB Bridge
Adds PCI Express external connectivity to AMBA 2.0 AHB-based SoCs more

Allows the DesignWare PCI Express port logic to bridge to the AMBA 2.0 AHB on-chip bus
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PCI Express to AXI Bridge
Adds PCI Express external connectivity to AMBA 3 AXI-based SoCs more

Allows the DesignWare PCI Express port logic to bridge to the AMBA 3 AXI on-chip bus
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1.1 PHY
Low power, small area PCI Express 1.1 PHY operating at 2.5 Gbps more

The low power PHY integrates high-speed mixed-signal custom CMOS circuitry The IP is compliant with the PCIe 1.1 specification and PIPE interface standard.
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2.0 PHY
High performance, low power PCI Express 2.0 PHY operating at 5.0 Gbps more

The low power PHY integrates high-speed mixed-signal custom CMOS circuitry. The IP is compliant with the PCIe 2.0 specification and PIPE interface standard
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3.0 PHY
High performance, low power PCI Express 3.0 PHY operating at 8.0 Gbps more

Compliant with the PCI Express 3.0 (8.0 GT/s), 2.0 (5.0 GT/s) and 1.1 (2.5 GT/s) specifications

Verification IP
Verifies PCI Express 3.0, 2.0, and 1.1 EP, Switch, and RC devices more

Verifies PCI Express endpoints, switch and root complex devices. The IP can be configured for verification at multiple levels including the 8b/10b and PIPE.
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