Getting your chips into volume production on a fast, predictable schedule becomes more and more difficult with each new process node. At advanced geometries, the risk of a protracted design cycle - and its associated cost burden - becomes a real threat to the health of your business.
The extraordinary levels of integration afforded by very deep sub-micron (VDSM) processes amplify the challenges in physical design. Closing timing in a predictable manner at both the block and chip levels requires a thorough understanding of physical effects. While timing, signal integrity, testability, and power issues are first order considerations, their interdependencies further complicate design closure. Leveraging deep expertise in the tools and specializing in RTL- to-GDSII design services, Synopsys consultants help you achieve an optimized block- or chip-level implementation in the fastest possible timeframe.
Through hundreds of projects and more than 15 years of working with our customers on their most challenging chip designs, Synopsys Professional Services has established a leading-edge design competency, with consultants skilled in the latest EDA technology and design practices. Synopsys consultants utilize world-class tools from Synopsys’ Galaxy Implementation Platform, a production-proven infrastructure including the Lynx Design System, and extensive design experience to augment your project team. We deliver project support from the earliest phases of implementation through tape-out, identifying and resolving bottlenecks and transferring methodology and best practices throughout the engagement. From block level optimization to full chip integration, from IP integration and constraints management to power optimization and chip finishing, Synopsys experts can help you optimize your design’s performance and accelerate your project schedules.
Synopsys’ Design Implementation Collaboration services include assistance with:
- Hierarchical budgeting and design planning
- SI-aware place & route
- Full-chip timing/SI closure, static timing analysis and sign-off
- Qualifying libraries, existing RTL and design constraints
- Generating and optimizing clock trees
- Power planning and optimization
- Full-chip extraction and in-design physical verification
- Chip finishing to tapeout
- Support for netlist, placed-gates, or GDSII manufacturing handoffs as well as concept-to-parts
- Adopting demonstrated methods and baseline scripts for follow-on project use
To get more information on how we can customize our services for you, please contact us or call your local sales representative.