 Hybrid Techniques Reduce Dynamic Power Consumption |
With the predominance of mobile devices, rising energy costs, and an awareness of green practices, power consumption has become a major concern for design engineers. When power consumption is analyzed, it breaks down into two main components: static or leakage power, which occurs naturally when components are idle and powered on; and dynamic power, which is the power consumed when components are switching. While both static and dynamic power remain important targets for power reduction, this paper will focus on only dynamic power, and explore ways to improve that metric.
Cary Chin, Synopsys |
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| Pain Management in Power Optimization: Best Practices for Reducing Power, Improving Productivity and Getting SoCs out the Door on Time and on Budget |
Power has always been an integral part of consumer electronics, but increasingly we can do more things with a single device. That trend, above all others, has moved power consumption from an afterthought to a critical part of the architecture of the processor, the SoC and even the end device itself.
Cary Chin, Synopsys |
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| Testing Low Power Designs with Power Aware Test |
The most important trend over the past decade for semiconductor design is the dominant requirement to reduce power consumption and power dissipation. Not only do competitive products require more functionality and higher performance, they must fit into increasingly smaller and more portable products.
Cy Hay, Product Manager, Synopsys |
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| Realizing Low Power IC Design: It Starts with the Clock Tree |
Designers and CAD engineers have the responsibility to implement high performance, high yield physical
designs. Now, market demands require these designs meet the same performance and yield goals
while also achieving the lowest possible power consumption. The fact that the clock network nominally
consumes 30% to 50% of a design’s power warrants a focus on low-power clock tree synthesis (CTS).
The challenge is to create an integrated, comprehensive flow that meets the technical objectives - highest
performance and lowest possible power - without sacrificing design closure.
Harvey Toyama, Implementation Group, Synopsys
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| Synopsys Eclypse Low Power Solution |
This white paper describes the key issues that designers face in reducing chip power dissipation, and outlines Synopsys’ approach to providing low power design solutions utilizing the open, industry-standard IEEE 1801™ “Standard for Design and Verification of Low Power Integrated Circuits.”
Cary Chin, Synopsys |
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| Eclypse Low Power Solution: Clock Tree Synthesis |
With the predominance of mobile devices, the rising cost of energy, and an increasing sensitivity to green practices, low power consumption has become a major concern for design engineers. This paper will outline some best practices for low power design and explain how IC Compiler, a key part of Synopsys’ Eclypse™ Low Power Solution, delivers low power clock tree synthesis (CTS) that concurrently achieves the lowest design power and the best possible performance and area.
David Hsu and Harvey Toyama |
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