Training

Courses
Training Options

Verification
Functional Verification Courses

	Formality	Learn to perform formal equivalence checking on designs that have been transformed in various ways from RTL to gate-level. Schedule

	HSPICE Essentials	This course will teach you the essentials of using HSPICE including how to set up and run a simulation, and how to perform AC, DC and transient analyses. Schedule

	HSPICE Advanced Topics	This course teaches HSPICE for statistical analysis and signal integrity applications including advanced components and syntax, , field solver and extracting S-parameters. Schedule

	HSIM	This course will teach you how to use HSIM and HSIMplus fastspice simulators for analysis of high performance analog, mixed-signal, memory and SOC designs. Schedule

	MAST Modeling	Learn to use Saber more effectively by understanding general device models, how to parameterize existing models, how to develop macro and simple device models. Schedule

	Nanosim	This course teaches the basics of the NanoSim engine and how to set up and run a simulation. NanoSim is a superset of TimeMill and PowerMill inclusive of all features. Schedule

	NanoTime	This course takes you from the introduction of fundamental concepts through advanced features of NanoTime for transistor-level static timing. The workshop will help you learn to use NanoTime to perform static timing analysis on large blocks and create .lib models for use in hierarchical analysis. Schedule

	NanoTime Ultra	This course takes you through advanced features of NanoTime Ultra for transistor-level static timing. The workshop will help you learn to use NanoTime Ultra to perform static timing analysis with PBSA, run signal integrity analysis, and run signal integrity delay analysis. Schedule

	SystemVerilog Assertions	This class teaches the key features of the SystemVerilog Asssertion language and its use in VCS, including how to create reusable, scalable assertions and assess the effectiveness of your testbench. Schedule

	SystemVerilog Testbench	In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS. Schedule

	SystemVerilog VMM	In this course, you will learn to apply the VMM Methodology using SystemVerilog language. It is recommended to take SystemVerilog Testbench workshop before this class. Schedule

	Saber	This course teaches engineers how to use the Saber Designer mixed-signal and mixed-technology suite of tools: Saber Sketch, Saber Simulator and CosmosScope. Schedule

	Vera	This course teaches how to write an OpenVera testbench to verify a device under test with coverage-driven random stimulus flow using VCS and Vera. Schedule

	OpenVera RVM	In this course, you will learn to effectively use the Verification Methodology Manual (VMM) based RVM classes. Schedule

RTL Synthesis
Design Synthesis Courses

	Design Compiler 1	This course covers the ASIC synthesis flow using Design Compiler. You will learn how to read, constrain and synthesize a complex design for area and timing. Schedule

	DFT Compiler 1	In this course you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and insert scan using top-down and bottom-up flows. Schedule

	Power Compiler	Use PowerCompiler to analyze and optimize average power consumption at the RT and gate levels. Use RTL Power Estimator to perform pre-synthesis average power estimation. Schedule

	Design Compiler Topographical/Graphical	This course covers recommended methodologies for bringing physical constraints into logic synthesis using Design Compiler Topographical/Graphical. Schedule

Sign-Off
Design Sign-Off Courses

	PrimeRail	This course introduces fundamental concepts to advanced features of PrimeRail for full-chip power grid reliability analysis that includes gate and transistor levels. Schedule

	PrimeTime PX	This class will show you how to use PrimeTime PX to effectively analyze Peak Power and Average Power in both UPF and non-UPF flows. Schedule

	PrimeTime 1	This course teaches you how to perform static timing analysis using PrimeTime. Quickly identify and debug your design violations by generating and interpreting timing reports. Schedule

	PrimeTime2: Debugging Constraints	This course teaches an efficient method to identify potential timing problems, identify the cause, and determine the effects of these problems. Schedule

	PrimeTime SI	The PrimeTime SI course teaches the techniques to increase the precision of your STA while taking into account crosstalk effects. Schedule

	StarRC	This course teaches the fundamentals of RC extraction and flows such as cell vs. transistor-level extraction, top-level vs. in-context extraction, Milkyway vs. LEF/DEF flow etc Schedule

	TetraMAX 1	In this course you will learn how to use TetraMAX to perform ATPG for stuck-at faults on a post-layout chip netlist for a scan design. Schedule

	TetraMAX 2: DSM Testing	This course will teach you how to perform at-speed testing as well as the "Launch on Shift" and "Launch on System Clock" techniques to detect an at-speed fault. Schedule

Physical Implementation
Design Implementation Courses

	IC Compiler 1	This course teaches how to use IC Compiler to perform placement, power, DFT, CTS, routing, SI and optimizations to achieve design closure for a SOC. Schedule

	IC Compiler 2 Clock Tree Synthesis	This course teaches how to use IC Compiler to perform pre-CTS checks and build clock trees to achieve good quality of results (QoR). Schedule

	IC Compiler 2: Hierarchical Design Planning	This course teaches how to partition a design into hierarchical sub-blocks and creating the floorplan, constraint and timing information required for implementation. Schedule

DFM
DFM & TCAD Courses

Basic TCAD Sentaurus

This course will introduce users to basic concepts of how to use Synopsys’ TCAD tools.
Schedule

Synplicity
FPGA Implementation Courses

	Synplify Pro & Premier	The course will familiarize new students with the FPGA design flow utilizing features of the Synplify Pro product. Schedule

	Identify	This course introduces concepts on full-speed hardware debugging using the Identify toolset which provides an "embedded HDL analyzer". Schedule

	Certify	This course introduces concepts on ASIC prototyping using the Certify ASIC Prototyping tool. Schedule

	Synplify DSP	This course shows users the Synpilfy DSP design flow including model creation, implementation and architectural exploration. Schedule

Flow and Methodology
Learn to apply a proven Synopsys methodology to your design

	Low Power Flow	This workshop will guide you through the complete Synopsys low-power flow (Eclypse) based on the industry-standard UPF language. Schedule

	Low Power Flow HLD (Front End)	In this course, using the Front-End Synopsys Eclypse Low Power Flow, you will synthesize, analyze, and verify a 65nm Multi Voltage (MV) design requiring shutdown. Schedule

	Low Power Flow P&R (Backend Flow)	This course teaches the design flow for back-end processing of a Multi-Voltage (MV) design using Synopsys’ Eclypse Low-Power Flow. Schedule

	OpenVera RVM	In this course, you will learn to effectively use the Verification Methodology Manual (VMM) based RVM classes. Schedule

	SystemVerilog VMM	In this course, you will learn to apply the VMM Methodology using SystemVerilog language. It is recommended to take SystemVerilog Testbench workshop before this class. Schedule

Public Classes
Instructor-led training is offered at Synopsys’ global training centers. Classes include both lecture sessions and the opportunity to practice what you learn in hands-on labs. Course Calendar

Private Classes
All standard Synopsys classes can be offered as private workshops for groups of 8 or more students. We also offer customized training designed to meet the unique needs of your design team. An expert Synopsys instructor will deliver your private class at a Synopsys training facility, at your location or via Webex®--whichever is most convenient for you. Contact us

Synopsys Virtual Classroom
The Synopsys Virtual Classroom—available as an option for private workshops—is a time- and cost- effective alternative to on-site training. The Virtual Classroom is particularly useful for geographically dispersed teams—allowing team members to efficiently train together regardless of location.

The Virtual Classroom is a web-based environment that delivers live, interactive training right to your desk, eliminating the need to travel to a traditional physical classroom. You can participate in lectures, ask the instructor questions and practice what you’ve learned with hands on labs through the EducationSphere environment--just as you would in a traditional class.

To schedule a Virtual Classroom workshop for your design team, Contact us.

On-Demand Training
Pre-recorded, self-paced training modules on a range of topics, including the latest tool features, design methodologies, and how to deal with common support issues are available on SolvNet. (a SolvNet userID is required).