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The Synplicity Business Group of Synopsys leverages its many years of experience to deliver a high-quality, high-performance, easy to use and technology--independent FPGA implementation solution. This solution provides FPGA designers with the fastest time-to-results for complex FPGAs, multi-vendor support, Area optimization for cost reduction, powerful design analysis and RTL debug, and 3rd party IP support.
- FPGA Synthesis
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Fast Timing Closure and Best Performance | |
- High Level Synthesis
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High Level Synthesis for FPGA and ASIC | |
- Simulation
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High-Performance Functional Verification | |
- Debug
| Integrated RTL Debug and Visibility Enhancement | |
| Identify |
Simulator-like Visibilty into Hardware Debug |
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| Identify Pro |
Debugging and Visibility Enhancement |
- ASIC Prototyping
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At-Speed Verification with Rapid Prototypes | |
| HAPS |
High-performance ASIC Prototyping System |
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| Certify |
Multi-FPGA Implementation and Partitioning |
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| Identify Pro |
Dubugging and Visibility Enhancement |
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| Synplify Premier |
Single-FPGA Implementation and Rapid Prototyping |
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| CHIPit |
Automated Rapid Prototyping |
- ASIC Verification Using FPGA-Based Prototypes
- As a part of Synopsys' Confirma Verification Platform, the Synplify Premier solution offers the most comprehensive system for implementing FPGA-based prototypes of ASICs and ASSPs including gated clock conversion and DesignWare support.
- Integration with Algorithmic Synthesis for DSP
- Tight integration with Synopsys’ high-level synthesis product (Synplify DSP) allows FPGA designers to rapidly explore and implement DSP algorithms in a range of FPGA architectures and vendors from a single model.
- Fastest time-to-results for complex FPGAs
- Unique timing-driven and graph-based physical synthesis technologies enable you to reach aggressive timing goals in the shortest amount of time.
- Multi-vendor support
- Synopsys’ technology independent FPGA implementation solutions allow you to quickly retarget your design to the FPGA architecture that makes the most sense for your project, at any time in the design cycle.
- Area Optimization for cost reduction
- The Synplify synthesis tools allow you to specify the performance you need, then the tool will work to reduce the logic required to achieve that performance providing the ability to fit your design in the smallest, least expensive part possible.
- Powerful design analysis and debug
- Analyze and debug where you design – in RTL. Instantly see a high-level graphical representation of your design that is linked back to the source code that produced it.
- 3rd Party IP
- Use of IP is increasingly important to FPGA designers. The Synplify family of products have integrated access to 3rd party IP for evaluation and integration into your designs.
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