IC Validator Datasheet

Overview
IC Validator is a signoff DRC/LVS tool that has been architected for in-design physical verification at leading-edge process nodes. It delivers excellent scalability for efficient utilization of available hardware, superior ease-of-use for the physical designer, and high programmability for easier runset development.

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IC Validator’s high performance physical verification engine substantially reduces the time to results through near-linear scalability across multiple CPU cores.
IC Validator is seamlessly integrated with IC Compiler to significantly reduce total physical verification time through in-design verification, stream-out reduction, incremental processing, and automatic error detection and correction. In-Design integration also enables fast, timingaware implementation of DFM such as metal fill.
IC Validator is fully qualified for DRC/LVS signoff at the current 45nm and 40nm process nodes as well as the emerging 32nm and 28nm nodes at major IDMs and foundries.

Benefits

Turnaround Time
Prevailing approaches to physical design today can be described as implementthen- verify, resulting in multiple time-consuming iterations between design and signoff. This cumbersome flow is due to the lack of signoff-quality physical verification during design implementation. At the 45nm technology node and beyond, the implement-then-verify flow is slow and may complicate convergence as layout corrections can alter key design metrics such as area, timing and power.

IC Validator is specifically architected for in-design physical verification, bringing the power of full signoff physical verification constraints into the design phase without imposing time-consuming stream in and stream out of layout data. Using in-design physical verification, DRC issues are caught much earlier in the design cycle, reducing or eliminating late-stage surprises close to tapeout. With in-design verification, specific layer, rules and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time. Design rule violations discovered during verification can be automatically fixed within the global timing and area context of the design, reducing the impact of the correction. In addition, chip finishing operations typically performed during physical verification, such as metal fill, are managed in a similar fashion. Working with IC Compiler, IC Validator’s in-design flow delivers significantly faster runtimes and dramatically reduces chip finishing iterations by performing signoff quality, timing-driven metal fill during the design phase.

Scalability and Throughput
The complexity of the physical verification task has grown substantially at the 45nm process node, and is getting worse at 32nm and beyond. To address the capacity and performance requirements of physical verification at these advanced nodes, IC Validator is architected for excellent scalability and efficient utilization of available hardware.

Multithreading: IC Validator’s multithreading approach significantly shortens execution time on modern multicore CPUs.

Scalability: IC Validator provides nearlinear scalability across a distributed computing network, supporting a 20x run time acceleration on a 25-cpu network and enabling completion of any physical verification task overnight.

Figure 1: IC Compiler GUI showing IC Validator-enabled Signoff DRC command

Enhanced Productivity with In-Design Physical Verification

Automatic DRC Correction
IC Validator’s seamless integration with IC Compiler enables an innovative layout auto-correction interface, which identifies DRC violations and initiates an automatic repair. The correction is applied by IC Compiler to alleviate the DRC error, then validated within IC Validator. This tight find-and-repair loop enables rapid discovery and repair of DRC errors, minimizing designer intervention and speeding time to tapeout.

Figure 2: IC Validator scalability

Incremental Layer-based, Rule-based and Area-based Verification
The combination of increasing design complexity, increasing design rule complexity and increasing design rule count have conspired to lengthen overall physical verification at 45nm and below. Complex design rules require relatively more effort to verify, increasing the cost of verification and delaying DRC closure. To accelerate physical verification time, intelligent incremental flows enabled by IC Validator and IC Compiler integration eliminate unnecessary checking by restricting verification to the specific layer, rule or design area that needs validation. Focusing the verification in this way would normally involve a complicated series of steps, such as streaming out the design and modifying the runset or command parameters prior to execution. The tight integration between IC Compiler and IC Validator eliminate these manual steps through a powerful tool dialog that allows the user to quickly select the rules, layers and region size for checking. This operation automatically limits the scope of the validation, speeding time to verification results. As a result of this tight verification loop, more verification runs can be performed early in the design cycle, greatly reducing the number of full design verification runs during signoff validation.

Incremental verification is especially important for ECO validation, which typically impacts a very small section of the design. Using a conventional flow, critical verification time can be wasted on checking the full chip even when changes were made to selected regions or layers. The in-design flow saves time by restricting the verification to only the layers and area affected by the ECO. As a result, the in-design flow significantly speeds verification without undue burden on the physical designer.

Figure 3: Native Layer-based or Rule-based Verification

Practical DFM
At advanced nodes, DFM steps such as metal fill are mandatory to ensure manufacturability and high yield. By introducing timing changes, post-design DFM can cause excessive iterations with design. ICC-ICV integration enables single-pass DFM implementation, such as metal fill. In addition, the fill runtime is significantly faster due to the scalability offered by IC Validator.

Figure 4: VUE error navigation

Error Visualization
To maintain efficient physical verification, rapid visualization and error correction are nearly as important as fast physical verification runtime. IC Validator includes the IC Validator VUE visualization tool, which provides an easy to use, intelligent error navigation and prioritization system for efficient review and correction of physical verification issues. Using IC Validator VUE, layout engineers can quickly and easily scan physical verification errors in IC Compiler environment, as well as other widely used layout editors. IC Validator VUE enhances productivity for physical verification engineers.

Custom Designer Integration
IC Validator works together with Synopsys’ layout editing tool, Custom Designer LE, to support a tightly integrated DRC and LVS-enabled custom design flow. Both IC Validator and Custom Designer fully support the SI2 OpenAccess database. In addition, Custom Designer is integrated with the VUE error navigator for rapid debug of DRC and LVS issues.

Signoff Ready at 45nm and 32nm

Foundry Qualification
Comprehensive foundry qualification is a necessary component of any successful physical verification solution. IC Validator is designed specifically for 45nm and smaller nodes, and is qualified and in use at 45nm, 40nm, 32nm and 28nm nodes at leading foundries.

Layout-vs-Schematic (LVS)
IC Validator LVS is qualified at leading foundries and works with other Synopsys tools such as StarRC™ to enable device and parasitic extraction. IC Validator simplifies extraction by implementing a single pass flow, providing a major performance increase over the double extraction flow of previous generation tools. The VUE and Shortfinder tools augment the LVS flow by working together with IC Validator LVS to speed the identification of errors such as text-level shorts, enabling rapid repair and revalidation.

Programmable PXL Language
The demanding requirements of physical verification at emerging nodes necessitate a new approach to runset development. IC Validator encapsulates an innovative new language, PXL, designed from the ground up to efficiently manage the complexities of physical verification at 45nm, 32nm and beyond. Powerful programming constructs enable simplification of the runset, resulting in fewer lines of code and easier runset maintenance.

Altogether, PXL adds power and flexibility while reducing cost of runset development up 10x.

Figure 5: IC Validator LVS Extraction Flow

Flexible Error Reporting
IC Validator incorporates a new application for customized DRC disposition and reporting. Using this feature, physical verification engineers can implement a custom DRC waiver system that supports the rapid categorization of DRC violations. Custom report generation is also greatly simplified. To speed time the analysis, DRC errors may now be reviewed as they are recorded as the DRC job continues to run. This approach speeds time to tapeout by enabling parallel debug and execution.

Interfaces and Platforms
Input and Output Data Formats:

Supported Platforms: