A common technique for saving dynamic power is to insert clock gates. Clock gates are elements that control the arrival of clock signals to sequential elements. If a condition can be found in which the sequential element does not need to load data, then power can be saved by blocking the clock signal. This can be performed via XOR self-gating, an effective technique for reducing dynamic power consumption.
Jonathan Ezroni, Corporate Applications Engineer, Synopsys

With Design Compiler 2010, RTL designers can now modify or create a floorplan within the familiar synthesis environment, saving costly iterations in the design flow.
Philip Issac & Liz Chambers Implementation Group, Synopsys

The most important trend over the past decade for semiconductor design is the dominant requirement to reduce power consumption and power dissipation. Not only do competitive products require more functionality and higher performance, they must fit into increasingly smaller and more portable products.
Cy Hay, Product Manager, Synopsys

Exponential growth in size and complexity of systems on a chip (SoCs), coupled with increasingly stringent quality mandates, necessitates an efficient and productive approach for register-transferlevel (RTL) designers implementing design-for-testability (DFT). Synopsys provides test technology embedded in synthesis, or “synthesis-based test”, to implement the key aspects of DFT for scan testing, boundary scan, embedded memory test, on-chip testing of high-speed blocks like USB and PCI Express® cores and connections to yield analysis.
Robert Ruiz

This paper highlights how use of concurrent optimization for multiple modes and at multiple corners (MCMM) with Design Compiler Graphical provides users with maximum productivity and post-route leakage savings.
Mary Ann White Implementation Group, Synopsys

Formality is an equivalence-checking solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. Formality delivers superior completion on designs compiled with DC Ultra.
Erin Hatch Formality CAE, Synopsys

Scan-based DFT is now the standard digital logic testing used on almost all SoC designs.
Cy Hay, Product Manager

Running automatic test pattern generation (ATPG) on a single processor may take a week or longer to complete, especially for very large designs and when testing at-speed fault models. Designers and test engineers need a straightforward way to reduce ATPG runtime by many factors and deliver working test patterns in days, not weeks.
Cy Hay, Product Manager

Exponential growth in size and complexity of systems on a chip (SoCs), coupled with increasingly stringent quality mandates, demand an efficient and productive approach for register-transfer-level (RTL) designers implementing design-for-testability (DFT).
Robert Ruiz Test Product Marketing Manager, Synopsys, Inc.

A predictable RTL to GDSII design flow is esential for the completing designs on time. Synopsys' DC Ultra(TM) topographical technology accurately prdeicts layout results, such as timing, area, and power during synthesis, and delvers a predictalbe RTL-to GDSII implementation flow.
Synopsys

Scan design, the ubiquitous design-for-test technology, is based on a relatively simple concept: One or more scan chains are constructed on a chip by serially tying together a set of internal registers and flip-flops.
Rohit Kapur & Robert Ruiz, Synopsys