 Faster Design Convergence with Design Compiler 2010 |
With Design Compiler 2010, RTL designers can now modify or create a floorplan within the familiar synthesis environment, saving costly iterations in the design flow.
Philip Issac & Liz Chambers
Implementation Group, Synopsys
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| Testing Low Power Designs with Power Aware Test |
The most important trend over the past decade for semiconductor design is the dominant requirement to reduce power consumption and power dissipation. Not only do competitive products require more functionality and higher performance, they must fit into increasingly smaller and more portable products.
Cy Hay, Product Manager, Synopsys |
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| Maximizing Leakage Savings with DC 2010.03 |
This paper highlights how use of concurrent optimization for multiple modes and at multiple corners (MCMM) with Design Compiler Graphical provides users with maximum productivity and post-route leakage savings.
Mary Ann White
Implementation Group,
Synopsys
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| Using TetraMAX® Physical Diagnostics for Advanced Yield Analysis |
Scan-based DFT is now the standard digital logic testing used on almost all SoC designs.
Cy Hay, Product Manager |
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| Multicore and Distributed Processing With TetraMAX® ATPG |
Running automatic test pattern generation (ATPG) on a single processor may take a week or longer to complete, especially for very large designs and when testing at-speed fault models. Designers and test engineers need a straightforward way to reduce ATPG runtime by many factors and deliver working test patterns in days, not weeks.
Cy Hay, Product Manager |
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| Techniques for Achieving Higher Completion in Formality® |
Formality is an equivalence-checking solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. Formality delivers superior completion on designs compiled with DC Ultra.
Erin Hatch
Formality CAE, Synopsys |
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| Maximizing RTL Designer Productivity for Implementation Design-for-Test |
Exponential growth in size and complexity of systems on a chip (SoCs), coupled with increasingly
stringent quality mandates, demand an efficient and productive approach for register-transfer-level (RTL)
designers implementing design-for-testability (DFT).
Robert Ruiz
Test Product
Marketing Manager,
Synopsys, Inc. |
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| DC Ultra Accelerating Design Closure |
A predictable RTL to GDSII design flow is esential for the completing designs on time. Synopsys' DC Ultra(TM) topographical technology accurately prdeicts layout results, such as timing, area, and power during synthesis, and delvers a predictalbe RTL-to GDSII implementation flow.
Synopsys |
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| DFTMAX Compression Backgrounder |
Scan design, the ubiquitous design-for-test technology, is based on a relatively simple concept: One or
more scan chains are constructed on a chip by serially tying together a set of internal registers and flip-flops.
Rohit Kapur & Robert Ruiz, Synopsys |
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