Design Compiler® in the Galaxy™ Implementation Platform maximizes your productivity with its suite of RTL synthesis and test solutions. The premier synthesis product, DC Ultra, lets you accurately predict post-layout timing, area and power during RTL synthesis, to significantly reduce costly and time-consuming design iterations. Design Compiler Graphical enables RTL designers to predict, visualize and alleviate wire routing congestion and perform floorplan prior to physical implementation. Additionally, it produces “physical guidance” to the IC Compiler place-and-route solution for tighter correlation and faster placement runtimes. The Design Compiler family also includes: the award-winning Galaxy Test solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler™, for power synthesis and optimization; the Formality® equivalence checker; and the DesignWare® library with its unequalled variety of synthesizable IP. These best-in-class, production-proven solutions are integrated to achieve the industry’s fastest and most predictable RTL-to-GDSII flow.