System-Level Design

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System-Level Design

Unmatched Productivity From System Design to Implementation

Synopsys provides a comprehensive portfolio of system-level products that bridge the gap from system design to implementation. These products include Innovator, Platform Architect and CoMET/METeor as Virtual Prototyping solutions enabling pre-silicon software development, verification and architecture exploration; System Studio and SPW for signal processing algorithm design and analysis; Synphony HLS for high-level synthesis to FPGA or ASIC; and the Saber® platform for designing and verifying power electronics, mechatronic systems, and wire harnesses. The tools are complemented by libraries that contain an extensive set of models to accelerate development. The Synopsys system-level products improve the productivity of the entire project team by addressing the challenges at the front-end of both hardware and software development flows.

Tools
Libraries
System-Level Catalyst Program

Virtual Prototyping
Accelerating Embedded Software Development more

	Innovator	Powerful tool for the creation, assembly, and execution of SystemC-based virtual prototypes for pre-silicon software development and software driven verification. DOWNLOAD DATASHEET

	Platform Architect	SystemC-based graphical environment for capturing the entire product platform and the dash board for initiating the platform analysis functions.

	CoMET and METeor	Design, simulate, analyze, and optimize complex embedded systems and quantitatively evaluate performance while running real software applications.

	System-Level Libraries	Portfolio of transaction-level models which serve as the building blocks of virtual prototypes. DOWNLOAD DATASHEET

	System-Level Services	Assistance with building transaction-level models (TLMs) and virtual prototypes for pre-silicon software development .

FPGA-Based Prototyping
Flexible, modular hardware for prototyping ASICs more

	HAPS	High-performance ASIC Prototyping System

	Certify	Multi-FPGA Implementation and Partitioning

	Identify Pro	Debugging and Visibility Enhancement

	Synplify Premier	Single-FPGA Implementation and FPGA-Based Prototyping

	CHIPit	High-capacity, high-performance ASIC Prototyping System

Architecture Development
SystemC platform capture and architecture analysis more

Platform Architect

Efficiently explore and optimize the system-level performance of SoC interconnect and memory subsystem architectures

Algorithm Design & Analysis
Digital Signal Processing Algorithm Design & Optimization more

	System Studio	Model-based design creation, simulation and analysis of complex, digital signal processing (DSP) algorithms. DOWNLOAD DATASHEET

	System Studio Libraries	More than 3000 ready to use models, supporting the analysis and design of protocols and standards in the wireless and digital signal processing domain

	SPW	The path from innovation to implementation of digital signal processing

	SPW Model Libraries	Model libraries to accelerate the design of communication systems, featuring the latest standards.

Processor Development
Accelerate the Design of Processors and Configurable Accelerators more

Processor Designer

Automating the design and implementation of custom processors and programmable accelerators

High-Level Synthesis
High Level Synthesis from Language and Model-based Design more

Synphony HLS

Language and model-based high level synthesis technology providing an efficient path from algorithm concept to silicon.

Mechatronics
Saber Accelerates Robust Design more

Saber Simulator

Simulation and advanced analysis of multi-domain systems to improve reliability and reduce physical prototyping of electro-mechanical designs.

Wiring Harness
Saber Harness for Complex Wiring Design more

Saber Harness

Design and verification capabilities for the creation of complex wire harnesses.

DesignWare System-Level Library
The Synopsys DesignWare® System-Level Library provides product development teams a broad portfolio of tool-independent transaction-level models (TLMs) for the creation of virtual platforms. The ability to parallelize the hardware and software development effort through virtual platforms significantly reduces the product design cycle and speeds time to market.

System Studio Model Libraries
The System Studio DSP model libraries consist of more than 3000 models, from simple to complex, supporting the analysis and design of protocols and standards in the wireless and digital signal processing domain. Accelerate your digital signal-processing design by using ready-to-go simulation models, and quickly create alternative solutions by modifying the existing models.

Saber Model Libraries for Mechatronic Systems & PCB Simulation
Access to proven models ensures design teams can accurately simulate complex systems. Saber provides in excess of 30,000 characterized models and model templates for mechatronic, power electronics, in-vehicle networking, and a wide range of component types.

High-level Modeling Library and IP
Synphony HLS provides a high level IP model library that is synthesizable into optimized RTL implementations. It includes common signal processing functions such as filtering (FIR, IIR), FFT transforms, math and CORDIC functions, signal operations, memories, and control logic. It simplifies fixed point design by utilizing vector and multi-rate simulation and analysis features of MATLAB and Simulink environments from The MathWorks.

The System-Level Catalyst Program promotes interoperability between system-level design vendors. Learn how specific System-Level Catalyst members help increase your design productivity, visit members web page by clicking on the company name in the chart on the main System-Level Catalyst webpage or in the list below. You can request information on the joint design flow on each program member’s web page.

System-Level Catalyst Program has members from a wide variety of electronic design automation (EDA) vendors, intellectual property (IP) vendors, embedded software companies and service providers, the program is designed to benefit mutual customers by advancing tool and model interoperability as well as the availability of system-level models and services.

Members for Virtual prototypes include:

Agilent	Axilica	Carbon
CebaTech	ChipVision	CoFluent
CriticalBlue	Doulos	EmSys
Forte	GreenSocs	Imperas
JEDA	Jungo	Lauterbach
MCCI	NoBug	Steepest Ascent
SDV	Synfora	Target Compiler
Tensilica		VaST