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A View from the Top: A System-Level Blog
This blog will deal not only with the shift towards adoption of virtual platforms but with ESL technologies in general.
F. Schirrmeister, J. Stahl, M. Serughetti, T. Schutter, P. Sheridan
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Observations and views from 3 of Synopsys’ top AMS/custom design technologists.
Fred Sendig, Kishore Singhal, Bob Lefferts
Verification Martial Arts
In SystemVerilog, unlike C, you don’t have to explictly free dynamically allocated class instances.
Janick Bergeron
The Standards Game
Hello, everyone interested in EDA interoperability and fans of The Standards Game. I’d like to invite you to join me at the 21st Synopsys EDA Interoperability Forum, sponsored by Sun Microsystems.
Karen Bartleson
All Synopsys Blogs
HSPICE SIG EVENT
Hear what industry leaders say about using HSPICE in today’s most challenging designs
HSPICE TIPS WEBINAR
Reduce simulation time without compromising HSPICE gold-standard accuracy
CUSTOMEXPLORER ULTRA WEBINAR
Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra
CUSTOMSIM WEBINAR
Extending Digital Verification Techniques to Mixed-Signal Designs
DAC 2011: AMS DINNER VIDEOLOG
SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification
News
Synopsys Collaborates with Sigrity to Accelerate Signal Integrity Analysis
eSilicon Selects Synopsys' Custom IC Design Solution and Tapes Out 28-nm Designs
LG Electronics Accelerates Analog Simulation by 10X with Synopsys CustomSim
Synopsys and GLOBALFOUNDRIES Collaborate to Deliver 65nm iPDKs
Synopsys Custom Design Solution Enables Moortec Semiconductor to Tape Out....
Synopsys and TSMC Collaborate to Deliver Custom Design Solution for 28nm....
Synopsys Advances Mixed-Signal Verification with New CustomExplorer Ultra
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All Synopsys News
Articles
How VHDL designers can exploit SystemVerilog
Synopsys tries to organize its efforts in EDA multiprocessing
Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
VMM application packages- the next level of productivity
IC verification key: ‘Do it step by step, don’t cut corners’
Nightmares in Functional Verification
Future Verification Appears Uncertain
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Blogs
A View from the Top: A System-Level Blog
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Verification Martial Arts
The Standards Game
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White Papers
MOS Device Aging Analysis with HSPICE and CustomSim
Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS
Automated Regression for Mixed-Signal Verification
De-risking Variation-aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE
IC Validator: Physical Verification for Analog Designs
Accelerating Analog Simulation with HSPICE Precision Parallel Technology
Utilizing Digital Techniques for Analog and Mixed-Signal Verification
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Webinars
Get the Most from Your HSPICE Simulation
Avoid EM & IR-drop Effects in Custom IP Blocks
Regression and Analysis for Mixed-Signal Verification
Jitter Analysis Using HSPICE Transient Noise Techniques
Mixed-Signal Design Verification Techniques
Advances in Circuit Analysis with Custom Designer SAE
Accelerate Analog Simulation with HSPICE
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Videos
DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
HSPICE SIG: A Converging Analog World: Silicon, Package and System
DAC 2010: Coping with Modern AMS Verification Challenges
DAC 2009: Coping with Modern AMS Challenges
DAC 2009: Solutions for Tough Verification Challenges
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HSPICE Essentials
NanoSim
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