Tutorial 1 (Session 20): Advanced Verification Techniques Using VMM 1.2
Sponsored by Doulos
Monday, February 22
1:30 p.m. to 5:00 p.m.
(Fir Ballroom)
Presenters:
Doug Smith, Doulos
Faisal Haque, Verification Central
JL Gray, Verilab, Inc.
Ambar Sarkar, Paradigm Works, Inc.
With verification complexity increasing for each new design, verification engineers must continuously take advantage of advances in verification methodologies to stay productive. The VMM methodology first introduced in 2005 and deployed on many successful designs has evolved to meet growing verification requirements. The latest release of VMM enables higher productivity with SystemC/SystemVerilog TLM2 support, enhanced block-to-system reuse, more ease-of-use features and an enhanced register abstraction layer.
Each speaker will focus on a set of new features in the latest release of the VMM methodology and show how they can be used to solve real-life verification challenges. This session will help verification engineers get maximum benefit from VMM 1.2 by providing application-oriented information on key VMM 1.2 features that will boost engineers’ productivity and encourage re-use throughout a project's life-cycle and across projects. Attendees will be provided with theoretical background, familiarity with extended VMM 1.2 features, and a selection of real-world examples of best-practice VMM 1.2 usage, giving them confidence to begin using those features in their own projects.
Tutorial 4 (Session 23): Experience with VIP Interoperability Best Practices
Sponsored by Accelera
Tuesday, February 23
8:30 a.m. to 12:00 p.m.
(Fir Ballroom)
Presenters:
Thomas Alsop, Intel Corp.
Edgar Jimenez, Freescale Semiconductor
Sharon Rosenberg, Cadence Design Systems, Inc.
Janick Bergeron, Synopsys
Accellera’s VIP-TSC released its Best Practices document in August 2009. This was a collective effort by the TSC members to address the real problem of integrating Verification IP components built using VMM or OVM base classes under single verification environment. It contains an entire chapter devoted to introducing the high level concepts of interoperability and component integration. It outlines a process that the verification environment writer can use to determine which cross-referenced best practice sub-chapter(s) applies to his/her specific integration challenge. The main chapter of the document contains 12 sub-chapters dealing with the most common interoperability issues from phase synchronization to data conversion, communication, and messaging. It also contains an API to outline the interoperability library.
The presenters will share their experiences using the recommendations in the Best Practices document on real life projects – what worked, what came up short and our insights into making it better. They will also present their thoughts on any additional efforts necessary to make the verification components/environments easy to interoperate.
Tutorial 5 (Session 24): FPGA-based Rapid Prototyping Made Easy – A Hands on Tutorial
Sponsored by Synopsys
Tuesday, February 23
8:30 a.m. to 12:00 p.m.
(Oak Ballroom)
Presenters:
Neil Songcuan, Synopsys, Inc.
Juergen Jaeger, Synopsys, Inc.
The success of large-budget ASIC projects depends on the up-front choices made for their verification. Because of the increase in design complexity, speed, and large amounts of embedded software in today’s designs, the choice of the hardware-assisted verification method to be used is more important than ever before. This technical hands-on tutorial, designed for SoC design and verification engineers, system validation engineers and software and firmware developers, will detail how rapid prototyping solves the challenges associated with traditional verification approaches and brings together all of the critical components into a complete and affordable solution that enables you to find even the hardest-to-find hardware bugs, start software development earlier in the design cycle and integrate hardware and software well ahead of chip fabrication.
To fully demonstrate how rapid prototyping is used for pre-silicon validation and software development, multiple laptops with pre-installed software and actual rapid prototyping boards will be available in a workshop lab environment. The tutorial is based on a synthesizable model of a 32-bit processor compliant with the SPARC V8 architecture and will guide users on how to take the design from implementation to full debug visibility. After completing this unique hands-on tutorial, users will have a comprehensive understanding of how the different components of an integrated software and hardware solution fit together into a seamless debug flow. Note: This tutorial is limited to 40 participants.
Sponsored Luncheon: Real-World Verification
Thursday, February 25
12:00 p.m. to 1:30 p.m.
(Pine/Cedar Ballroom)
Presenters: [TBA]
Synopsys invites you to join us for lunch and a highly informative session covering the latest verification trends, challenges and solutions. You will hear leading industry experts discuss complex real-life verification challenges and present insights into best practices that help address them. This luncheon provides a valuable opportunity to learn about new innovations in verification technology that enable improved performance and productivity. If you are a verification engineer or manager, you won’t want to miss this special event.
In addition, Synopsys will be participating in the following technical sessions at DVCon 2010:
Back to DVCon 2010 web site