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Power Intent Verification For Low Power Designs Using ESP-CV
ESP-CV is a tool designed to perform functional equivalence checks between two different design representations. The new power intent verification features in ESP-CV provide the ability to verify various types of power management circuitry used in low power designs. These designs may be described as Verilog behavioral models, RTL, gates, transistors, or a SPICE netlist.
Clay McDonald, R&D Manager, Implementation Group, Synopsys; Dave Hedges, CAE, Implementation Group, Synopsys
Sep 15, 2010 | | | Static Verification Throughout the Low Power Design Flow
Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010 | | | Efficient & Accurate Memory Timing & Power Analysis using CustomSim
With the growing complexity of device models and the increasing impact on timing and power measurements from physical layout effects, accurate memory verification within a reasonable timeframe is a necessity. This webinar highlihgts memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time. Learn how Synopsys’ CustomSim™ solution is being used today for accurate and efficient memory timing and power analysis.
Bradley Geden, Product Marketing Manager, Synopsys
Dec 16, 2009 | | | Everything You Always Wanted to Know About Low Power Verification
An understanding of the impact on verification from the deployment of low power design techniques is key to successful verification. Learn why verification has changed for low power designs and how Synopsys' VCS with MVSIM and MVRC comprehensively and accurately meet these challenges.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Prapanna Tiwari, Corporate Applications Engineering Manager, Synopsys
Aug 11, 2009 | | | A Structured Methodology for Verifying Low Power Designs
In this webinar, we focus on the bug types that are new to low power design and introduce a structured and reusable methodology highlighting VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs.
Krishna Balachandran, Director of Low Power Verification Marketing, Synopsys; Srikanth Jadcherla, Group Director of R&D, Synopsys; Janick Bergeron, Synopsys Fellow, Synopsys
Aug 11, 2009 | | | Increase Design Confidence with CustomSim
Learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement.
Synopsys
Apr 28, 2009 | | | Verifying Complex Power-managed Designs
An overview of approaches that address the difficult task of verifying low power designs.
Synopsys
Dec 18, 2008 | | | Leakage Mitigation in ARM Processor-based Systems
Leakage mitigation techniques such as power gating, state retention and dynamic threshold scaling have been shown to significantly reduce standby power consumption.
Alan Gibbons, Principal Engineer, Synopsys; John Biggs, Consultant Engineer, ARM
Dec 18, 2007 | | |
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