Overview
Visit Synopsys at the online EE Times virtual conference to learn about our comprehensive software-to-silicon verification solution for early software development & architectural exploration, analog & digital functional verification and hardware-assisted system validation. Find out more about our innovative verification tools, IP, services and methodologies addressing key SoC development challenges, and check out the informative panels and chat sessions in which Synopsys participated.

Panels and Chat Sessions

Verification: SoC Verification Challenges
Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive
Synopsys panelist: Janick Bergeron, Fellow

Summary: Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. One way to address this challenge is to adopt a reuse-oriented, coverage-driven verification methodology. In the case of ASIC-based SoCs, the Verification Methodology Manual (VMM) for System Verilog — jointly authored by IP provider ARM and tool vendor Synopsys – is just one methodology. What about when designers approach verification based on their own design flows? What special verification tools and flows are available for FPGA-based SoCs? Can point tools address any "EDA holes" in the large ASIC- and FPGA-based SoC design flows? Architecture-related verification, RTL debug, Formal Verification, and Verification in light of IP design re-use will be covered.

Analog/Digital Integration: Integrating Analog and Digital IP onto an SoC
Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive
Synopsys panelist: Ralph Morgan, Vice President of Engineering

Summary: Depending on the SoC implementation strategy (ASIC- or FPGA-based), there are different considerations when it comes to integrating analog and digital IP. An ASIC-based SoC requires attention to the details of the design, less automation with regard to placement and routing, and more handcrafting of the transistors and associated resistive and capacitive elements. By comparison, designers work at a higher level of abstraction in the case of an SoC implemented using a mixed-signal FPGA technology. In both cases, however, there are common concerns... Can the various analog and digital simulators communicate with each other effectively? How can designers take full advantage of available tools for the intricately specific applications they are designing for? How do ASIC- and FPGA-based SoC design flows differ for different application areas? These and other design flow integration issues will be discussed by tool developers, chip designers, and FPGA vendors.

Verification Live Chat Session: System Prototyping – Virtual, FPGA or Hybrid?

Summary: To accelerate project cycles, hardware teams try to start hardware/software validation, hardware verification and interface tests to real-world stimulus as soon as possible. Virtual platforms and FPGA-based rapid prototypes are just two of the alternative engines to execute your design prior to RTL and silicon availability. Does the emergence of virtual prototyping mean the end for FPGA-based prototypes?  Will the hardware prototype continue to live on as an integral part of the SOC design cycle? Will hybrids of virtual and hardware prototypes be the answer? Join this chat session to discuss with our experts on the future of system prototyping.

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