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2007

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2005

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User Papers

A5: NanoTime: The Next Generation Transistor-Level Analysis Solution for Custom Design

Bone: Custom Design Sizing Optimization Flow using NanoTime (1st Place - Best Paper)
Author(s): Gideon Reisfeld, Gregory Zabolotov [Intel]

Paper

Presentation

B1 - Verification Methodology

Analyze your OpenVera Code. Facilitate Code Reuse through Coding Guidelines and Code Documentation
Author(s): Yossi Ginzburg, Eyal Skulsky [Qualcomm]

Paper

Presentation

Chip Level Methodology for Fully Reuse Block Level Environments
Author(s): Shlomi Sperber [TI]

Paper

Presentation

Generic RVM Infrastructure
Author(s): Amit Pessach, Rachel Menes [Cisco]

Paper

Presentation

B3 - Physical Design

A PrimeTime Based Net-Switching flow
Author(s): Alexander Sudakov, Efrat Rachevsky [Marvell]

Paper

Presentation

MTC – Synthesis with Minimal Timing Constraints for Early Design
Author(s): Yossi Avrahami, Eyal Laufer [Intel]

Paper

Presentation

Resolving Critical Formal Verification Issues via Synopsys SVF
Author(s): Amit Barzilay [Mplicity]

Paper

Presentation

The Advantages of Using PrimeTime Distributed Multi Scenario Analysis (DMSA)
Author(s): Moshe Ashkenazi, Rafy Diaz [Texas Instruments]

Paper

Presentation

B5 -Analog Mixed-Signal

HSIM-VCS-SystemVerilog Verification Flow for Image Sensor Innovative Chip Design
Author(s): Vladimir Polyak [Advasense], Isaac Zafrany [Synopsys]

Paper

Presentation

Report Manager - Visualizing of HSIM Circuit Checks Results
Author(s): Ronen Moldovan [Saifun]

Paper

Presentation

C1 - Functional Verification Techniques

Are you Satisfied with your Constraints? Eight Ways to Misuse Vera Solver
Author(s): Yossi Ginzburg, Eyal Skulsky, Ziv Baum, Tzahi Sabo [Qualcomm]

Paper

Presentation

From Tools to Flow: Low Power Architecture Verification Using System Verilog
Author(s): Arik Rachevsky [Marvell]

Paper

Presentation

How to Code Functional Coverage in SystemVerilog
Author(s): Akiva Michelson [ACE Verification]

Paper

Presentation

C3 - Taming the ECO Beast: Synopsys’ ECO Solution Overview

Beyond the Human ECO Compiler
Author(s): Itai Yarom [Intel]

Paper

Presentation

Low Impact ECO Methodology
Author(s): Dan Saad [Texas Instruments]

Paper

Presentation

C4 - Gate-Level Power Analysis using PrimeTime-PX

Primetime-PX Integration in Zoran Power Flow
Author(s): Elon Rot [Zoran]

Paper

Presentation

C5 - Process Variation and Standard Cell Libraries

Characterization: The Key to Accurate Simulation
Author(s): Alex Weinberg , Boris Mishori [Tower Semiconductor]

Paper

Presentation

Tutorials

Variation-Aware Static Timing Analysis and Extraction
Author(s):

Tutorial

ICC based Pilot Physical Design Flow
Author(s):

Tutorial

NanoTime
Author(s):

Tutorial

Building an Application Interface for PCI Express: A Case Study Using AXI
Author(s):

Tutorial

Accelerate Time to Entitled Yield with PrimeYield Lithography Compliance Check
Author(s):

Tutorial

The Industry's Leading YMS Solution
Author(s):

Tutorial

Latest and Future Technologies in Low Power Design
Author(s):

Tutorial

HSIMplus and Mixed-Signal Solutions for Nanometer IC Design
Author(s):

Tutorial

Software Schedules Dominating Your Time-to-Market? – Adopt Virtual Platforms!
Author(s):

Tutorial

Design for Yield – The Foundry View
Author(s):

Tutorial

Optimizing for Design-Yield with IC Compiler
Author(s):

Tutorial

PrimeTime-PX
Author(s):

Tutorial

HSPICE Monte-Carlo and DCmatch Statistical Analyses
Author(s):

Tutorial

Mixed-Signal / Analog IP at 65 nm and Below
Author(s):

Tutorial

Panel Presentation

Panel Presentation

Formally specifying with SVA
Author(s):

Paper

System Verilog and VCS Update
Author(s):

Paper

System Verilog High Level Abstraction vs. Implementation
Author(s):

Paper

System Verilog Verification Methodology
Author(s):

Paper

Time to Quality: The Challenge of Verification Efficiency
Author(s):

Paper

Verification of Low Power Designs
Author(s):

Paper

Keynote speech

Keynote Speech
Author(s): Guri Stark [Synopsys]

Paper