HELPING YOU DESIGN THE CHIP INSIDE Products and Solutions ---------- SOLUTIONS ---------- Eclypse Low Power Solution Galaxy Design Platform • Design for Low Power • Design for Test • Design for Yield • RTL Synthesis • Physical Implementation • Sign-Off • Liberty CCS • SDC • Milkyway Discovery Verification Platform • Analysis and Debug Tools • Low-Power Verification • System Analysis & Design • Smart RTL Verification • Functional Equivalence Checking • Mixed-Signal • Languages Intellectual Property (IP) • DesignWare Library • DesignWare Verification IP • DesignWare Cores • DesignWare Star IP • DesignWare Foundry Libraries • IP Reuse Tools Design for Manufacturing • Design-Yield Analysis • Mask Synthesis • Mask Data Preparation • Lithography Verification • TCAD • Manufacturing Yield Management Professional Services • Tool and Methodology Deployment • Pilot Design Environment • Flow Optimization • Implementation • Verification Consulting • Concept to Parts • Core Hardening ---------- PRODUCTS ---------- BSD Compiler: Test synthesis Cadabra: Cell creation Calibration Library CATS: Mask data preparation Circuit Explorer: Analysis & Optimization coreAssembler coreBuilder coreConsultant CosmosLE: Layout design environment CosmosScope: Waveform analysis CosmosSE: Schem. design environment DC Ultra: RTL synthesis Design Analyzer: RTL synthesis Design Compiler: RTL synthesis DesignWare: Design & verif. IP DesignWare Virtual Platforms DFT Compiler MAX DFT Compiler: Test synthesis DSSA Sentry Enterprise: Layout editor ESP: Transistor-level Equivalence Checking Formality: Funct. equiv. checking Hercules: Physical verification HSIM HSPICE: Accurate circuit simulation IC Compiler IC Workbench Innovator: SoC / system modeling JupiterXT: Design planning Leda: RTL checker Library Compiler: Library compilation Liberty NCX: CCS Characterization Magellan: RTL formal verification Memory Solution Milkyway: Design database MVRC MVSIM NanoChar: 90 nanometer & below characterization NanoSim: Fast circuit simulation NanoTime Odyssey Defect/Odyssey YMS Paramos Pilot Design Environment Pioneer-NTB: SystemVerilog testbench automation Power Compiler: Power optimization PrimePower: Power analysis PrimeRail PrimeTime PX PrimeTime: Static timing analysis PrimeTime SI: Signal integrity analysis PrimeYield Tool Suite Proteus OPC PSM-Create & PSM-Check Raphael Raphael NXT Recipe Manager and Editor (RME) Saber: Multi-tech. simulation Scirocco: VHDL simulation Seismos Sentaurus Device Sentaurus Lithography Sentaurus Process Sentaurus Structure Editor Sentaurus TFM Sentaurus Topography Sentaurus Workbench SiVL-LRC: Lithography verification SpiceCheck SpiceExplorer Star-RCXT: Full-chip RC extraction Star-RCXT VX Star-SimXT: Fast circuit simulation System Studio: DSP algorithm design Taurus-Medici Taurus-TSuprem4 TestChip Products TetraMAX: ATPG VCS: Comprehensive RTL Verification VCS MX: Mixed-HDL simulation Vera: Testbench automation WaveView Analyzer DESIGN IMPLEMENTATION VERIFICATION INTELLECTUAL PROPERTY DFM/TCAD DESIGN SERVICES  RECENT FINANCIAL NEWS Synopsys Posts Financial Results for Q2 Fiscal Year 2008 Q2 FY2008 Financial Supplement Q2 FY2008 Conference Call Transcript Q2 FY2008 Webcast Advisory Synopsys Completes Acquisition of Synplicity, Inc. Synopsys Acquires Sandwork Design, Inc. Intel Selects Synopsys As Its Primary EDA Supplier Synopsys Completes Acquisition of MOSAID Semiconductor IP Assets Synopsys Acquires ArchPro Design Automation  EARNINGS CALL WEBCAST   Synopsys Q2 FY2008 Earnings Call on May 21, 2008  OTHER FINANCIAL NEWS 2008 Form 10-Q Quarter 1 Proxy 2008 2007 Form 10-K/A 2007 Form 10-K Financial Press Releases  INVESTOR PRESENTATIONS   Cowen and Company 20/20 TMT Conference (5/30/2008)   Morgan Stanley Technology Conference (3/5/2008)   D.A. Davidson Conference (2/22/2008) Investor Relations Welcome to Synopsys Investor Relations     Synopsys Q2 FY2008 Earnings Call on May 21, 2008      Investor Information   Financials Analyst Coverage Calendar of Events Frequently Asked Questions Online Printed Materials Request Form Contact Investor Relations Annual and Quarterly Reports Financial Press Releases SEC Filings Section 16 Filings 10-Ks, 10-Qs, Other SEC Filings   Company Information   Community Outreach Company Profile Executive Management Stock Quote and Financial Information EDA Industry Primer EDA Consortium Community Relations Outreach Foundation University Program   Corporate Governance & Values   Stock Quote (Symbol: SNPS) Our Commitments Code of Ethics and Business Conduct Corporate Governance Guidelines Board of Directors Board Committees Performance Compensation Last Trade : 23.48 Last Trade At: 7/3/2008 1:00pm ET Change : -0.27 (change%) Open : 23.84 Day's Range : 23.425 - 23.88 Volume : 1126514 *Quote delayed about 15 minutes The press releases contained on our website were made as of the date given in the press releases and, as such, may not continue to be accurate or complete as of a subsequent date.   Some documents in the Investor Relations section require that you have Adobe Acrobat Reader® installed in order to view files in PDF format. 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