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System-Level Design Signal processing algorithm design, high-level synthesis, virtual prototyping, mechatronics and wiring harness		Manufacturing Mask synthesis and data prep, lithography simulation and verification and yield management

Verification High-performance system, RTL, equivalence checking, and mixed-signal verification solutions		TCAD Process and device simulation solutions for technology development and manufacturing

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Interface IP Standard interfaces for SoC designs such as USB, PCIe, DDR, SATA, HDMI, MIPI and more		Logic Libraries SiWare Logic and ASAP Logic standard cell libraries for a wide array of applications and process technologies

Analog IP Analog IP such as audio codecs, data converters, touch screen controllers, video analog front-end, clock sources and sensors		Configurable Cores ARC cores, ARC Sound family, ARC Video family, configurable extensions and Sonic Focus enrichment software

Embedded Memories Embedded memory solutions including embedded SRAMs, embedded non-volatile memory and embedded test and repair		SoC Infrastructure IP DesignWare Library, minPower Components, verification IP, Integra on-chip communications, Integra memory controllers

Accelerate time from idea to implementation ready RTL


Algorithm Design & Analysis High performance, model-based signal processing algorithm design, and high level synthesis technology		Virtual Prototyping Software models of complete systems enabling early and concurrent development of hardware and software

Architecture Development Efficient exploration and optimization of system-level performance for SoC interconnect and memory subsystem architectures		FPGA-Based Prototyping Modular, high performance hardware solutions enabling at-speed hardware/software development, validation and debug

Processor Development Unified development of application-specific processors, programmable accelerators and software tool chain		Saber Behavioral design, modeling, and simulation for power electronics, multi-domain systems, and wire harnesses

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Tool and Methodology Adoption Take full advantage of the latest features and methodologies available in Synopsys' tools		Design Implementation Leverage tapeout-proven flows and project experience to get your chip done

SoC Design & Verification Achieve rapid design closure by applying best practices in system-level design, RTL creation, FPGA-based prototyping, and functional verification		Low Power Optimization Implement low power implementation and verification techniques to optimize your chip's power consumption

Design Flow Deployment Optimize your design flow to address the latest design challenges		Predictable Silicon Sign-Off Improve ASIC handoff with early optimization for physical effects

Solutions for Semiconductor and System Design


Eclypse Low Power Solution The perfect alignment of technology, methodology, IP, services, and industry standards to address advanced low power design		Discovery Verification Platform An integrated portfolio of functional, AMS, formal and low-power verification tools

Galaxy Implementation Platform A comprehensive solution for cell-based and custom IC implementation		Synplicity FPGA Design Solution Comprehensive toolsets, methodologies, and services to address FPGA design requirements

Industry Solutions Tailored solutions for automotive, memory, mil/aero, mobile devices & end-product categories		Lynx Design System A highly integrated, production-ready IC development platform

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Training Training courses on Synopsys� tools and methodologies		Global Support Centers Open a support issue online

SolvNet Get instant online access to the self-help support resources you need		Licensing, Installation & Compute Platforms The latest information about how to install, upgrade and manage your Synopsys licenses

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Synopsys Users Group (SNUG) Technology users and product experts exchange ideas at SNUG conferences		University Program Resources for teaching IC design: how to apply to our program, curriculum, articles, support and training, and much more

Partners Collaborating to provide advanced reference flows, design kits, libraries, IP and methodology		Interoperability EDA tools working together for customer satisfaction and success

Blogs & Forums Insights from the experts, open forums for global Synopsys community		Conversation Central Join us the third Thursday of each month to join the conversation!

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VERIFICATION IP

DESIGNWARE VIP ALLIANCE - MIPI HSI

DesignWare VIP Alliance - MIPI HSI

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Analog IP Selector

The MIPI HSI VMM based Verification IP (VIP) is compliant with the latest MIPI HSI physical layer specification Version 1.01.00. MIPI Specifications establish standards for hardware and software interfaces between the processors and peripherals typically found in mobile terminal systems.

The MIPI HSI VIP is an interface between an applications processor and cellular modem. It can be used to verify bothTransmitter and/or Receiver of MIPI HSI physical layer.

eInfochips VMM based SystemVerilog MIPI HSI Verification Component is based on the layered architecture of object oriented programming that allows coverage driven verification suitable for verifying transmitter and/or receiver of DUT.

For more information on eInfochips' MIPI HSI VIP, click here.

Highlights

Key Features:

Supports Synchronized, Pipelined and Receiver Real Time Data Flow
Supports both type of transmission modes on transmit interface -

Stream transmission mode
Frame transmission mode

Random as well as user defined configuration setup to hit particular scenarios. (e.g.
Channel Descriptor Field)
Functional Coverage
Error Injection Capability on Transmitter Interface

Missed clock cycles
Additional clock cycles
Signal error

Run-Time Configurability

For Transmitters

Data Rate Change

For Receivers

Data rate change
Time-out counter ON/OFF
Time-out counter value
Tailing-bit counter ON/OFF
Tailing-bit counter value
Frame burst counter ON/OFF
Frame burst counter value

Deliverables:

MIPI HSI VIP encrypted code
Documentation - User Guide, Release Notes
Sample Test cases