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The Good? The Bad? The Ugly? IP Perspectives from Vendor to SoC Integrator
While the IP landscape will always look different when seen through the eyes of SoC designers, integrators and IP vendors, these players gain a significant advantage if they see each others’ roles more clearly. This paper explores the perspectives of three such players and their approach to working with mixed-signal IP. After taking in each perspective, life with IP might be a little easier for everyone.
Solving the Integration Challenges for USB-Enabled Designs
Today's IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for use in a wide variety of applications—including portable consumer products. Power consumption and small form factors are thus key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. This paper provides insights into dealing with these issues and profiles the USB IP choices available from Synopsys.
DDR SDRAM: A Low Cost, Yet Increasingly Complex Off-Chip Memory Solution for SoCs
Almost everyone knows that the bulk of DRAMs produced end up in desktop and laptop computers just like the one used to write the whitepaper. In fact, approximately 90% of all DRAMs are used in computers – leaving the remaining 10% as square pegs pounded into round holes when used as off-chip memory for SoCs. As the number of SoC designs requiring an interface to external memory increases, the modern DDRn SDRAM memory interface (DDR, DDR2, DDR3) offers security of supply, high storage capacity, low cost and reasonable channel bandwidth, but comes with an awkward interface and complicated controller issues.
Understanding the Fundamentals of PCI Express
PCI Express® - or PCIe® - is a high performance, high bandwidth serial communications interconnect standard that has been devised by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) to replace bus-based communication architectures, such as PCI, PCI Extended (PCI-X) and the accelerated graphics port (AGP). The objective of this white paper is to equip the reader with a broad understanding of PCI Express and the design challenges essential to successful PCIe implementation.
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