Insight News Issue 2, 2010

Synopsys' IC Compiler Widely Deployed at MediaTek
Synopsys announced that MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multimedia solutions, has standardized on Synopsys' IC Compiler physical design solution, a key component of the Galaxy™ Implementation Platform, to deliver best performance, power and area on MediaTek's leading-edge wireless communications chips. IC Compiler's advanced placement, timing and power optimization along with its tight correlation to signoff has contributed to faster design closure. [ more ]

Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC’s 65 Nanometer LL Process Technology
Synopsys announced the immediate availability of Synopsys’ silicon-proven and USB logo-certified DesignWare® USB 2.0 nanoPHY intellectual property (IP) for SMIC’s 65 nanometer (nm) low-leakage (LL) process technology. As a leading provider of complete IP solutions for the USB 2.0 interface including controllers, PHY and verification IP, Synopsys continues to help designers lower integration risk by providing high-quality IP that is proven interoperable and compliant to the USB 2.0 standard specification. [ more ]

Latest Synopsys IC Compiler Release Delivers More Than 2X Speed-Up, Enhanced In-Design Technology and Production Support for 28/32nm
Synopsys announced the availability of IC Compiler 2010.03, a physical implementation solution delivering up to 2.5X faster performance on multicorner/multimode (MCMM) designs, and enhanced In-Design technology for faster design closure. IC Compiler's In-Design technology helps prevent late-stage surprises by enabling signoff-accurate static timing analysis, rail analysis and physical verification during design. The new software release has production support for all known 28/32-nm design rules for major foundries, with several customer tapeouts underway. [ more ]

Synopsys Unveils Ethernet Controller IP With New Audio Video Bridging Feature
Synopsys announced the immediate availability of the DesignWare® Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features. The DesignWare Ethernet IP solution supports the new IEEE 802.1AS and 802.1-Qav version D6.0 specifications. These specifications enable efficient networking of streaming audio video (AV) applications through IEEE 802.1 networks found in consumer electronics, automotive AV and professional sound system products. Synopsys' DesignWare Ethernet QoS Controller, which supports 10/100/1G data transfer speeds, allows designers to develop system-on-chips (SoCs) that deliver time-synchronized, low-latency audio and video over Ethernet networks with exceptional quality-of-service while retaining compatibility with legacy networks. [ more ]

Synopsys Launches Industry’s First MIPI® DigRF(SM) v4 IP
Synopsys announced the immediate availability of the DesignWare® MIPI® 4G DigRF(SM) Master Controller IP. By complementing its current silicon-proven DesignWare MIPI 3G DigRF Controller and PHY IP, Synopsys becomes the first vendor to offer a comprehensive IP portfolio for both the MIPI DigRF v3 and v4 standards. The configurable MIPI 4G DigRF Master Controller is compliant to the recently ratified MIPI DigRF v4 1.00 specification and enables designers to reliably implement the new standard. In addition, Synopsys is developing the DesignWare M-PHY(SM), the physical layer for the MIPI DigRF v4 interface, in parallel with the ratification of the specification. A single-vendor solution enables designers to lower the risk and cost of integrating the DigRF interfaces into baseband ICs (BBICs) and application processors, while speeding time-to-market of advanced LTE and Mobile WiMAX system-on-chips (SoCs). [ more ]

Synopsys Wins Multiple EDN Innovation Awards
Synopsys was selected as the winner of EDN Magazine's 2009 Innovation Award in two product categories. The winning Synopsys products are DesignWare® SuperSpeed USB (USB 3.0) IP and IC Validator for In-Design physical verification with IC Compiler. The winning products and technologies, which were selected by EDN readers and editors for having shaped the semiconductor industry during the past year, were announced on April 26th in San Jose, Calif., at EDN's 20th Annual Innovation Awards ceremony. [ more ]

New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces
Synopsys announced the availability of the high-performance DesignWare® Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and LPDDR2 SDRAM standards. The DesignWare Universal Memory Controller helps reduce both the latency and silicon area by up to 50 percent compared to Synopsys' previous generations of DDR memory controllers thus improving the DRAM interface performance and reducing overall chip costs. The DesignWare Universal Protocol Controller provides efficient DDR control and protocol translation for applications without the need for a multi-ported memory controller. Both controllers deliver memory system performance of up to 2133 Mbps, the maximum data rate of the DDR3 standard, and offer a broadly utilized DFI 2.1-compliant interface to the DDR PHY. Furthermore, the Universal DDR Memory and Protocol Controllers enable designers to easily integrate multiple DDR interfaces into one design servicing a range of products spanning applications such as consumer electronics, mobile, network computing and automotive with less risk and improved time-to-market. [ more ]

Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed Signal FPGAs
Synopsys announced enhanced FPGA synthesis support is available for Actel Corporation's (Nasdaq: ACTL) new SmartFusion™ intelligent mixed signal FPGAs. Synopsys' Synplify Pro® FPGA synthesis tools have been enhanced to offer advanced support and timing optimization for the flash-based FPGA architecture that provides the programmable digital portion of the SmartFusion devices. [ more ]

Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems
Synopsys introduced the HAPS®-60 series of rapid prototyping systems—a comprehensive solution that eases complex SoC design and verification challenges. The HAPS-60 series, part of the Confirma™ Rapid Prototyping Platform, is an easy-to-use and cost-effective rapid prototyping system that enables early hardware/software co-verification and system-level integration at near-real-time run-rates, using at-speed, real-world interfaces. Built with the latest Xilinx Virtex®-6 devices, the HAPS-60 series combines performance, capacity, pre-tested IP and advanced verification functionality to deliver the most comprehensive prototyping system on the market. [ more ]

eSilicon Joins Synopsys' IP OEM Partner Program
Synopsys announced that eSilicon has joined the Synopsys IP OEM Partner Program. eSilicon has had a successful history using DesignWare® IP which includes the completion of 200 designs with 100 percent first-pass silicon success utilizing Synopsys' broad portfolio of high-quality IP solutions such as DesignWare Library, USB, PCI Express®, DDR, SATA, Ethernet, HDMI, MIPI IP including 3G DigRF, CSI-2 and D-PHY, data converters and audio codecs. [ more ]

Synopsys Expands IP OEM Partner Program with Two New Members
Synopsys announced that eSilicon and Brite Semiconductor have joined the Synopsys IP OEM Partner Program along with renewed members Global Unichip and Open-Silicon. Through the IP OEM Partner Program, members standardize on Synopsys' broad portfolio of silicon-proven DesignWare® interface and analog IP such as USB, PCI Express®, DDR, HDMI, SATA, Ethernet, MIPI IP including 3G DigRF, CSI-2, D-PHY, data converters and audio codecs for their system-on-chip (SoC) designs. By enabling member companies to access a wide range of interoperable IP from a single supplier, Synopsys helps them and their end-customers speed time-to-market and reduce risk for their complex SoC designs. [ more ]

Synopsys Recognizes Technical Excellence at 20th Annual SNUG San Jose Conference
Synopsys announced the Best Paper Awards for the twentieth annual Synopsys Users' Group (SNUG) San Jose conference, held in Santa Clara, Calif. on March 29-31. First place was awarded to Alvin Loke, Dru Cabler, Chad Lackey, Tin Tin Wee and Bruce Doyle of AMD and Zhi-Yuan Wu of GLOBALFOUNDRIES for "Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design"; Alvin Loke won the Best First-time Presenter Award for presenting this paper. Second place was awarded to Gerard M. Blair of LSI Corporation for "Hold is not setup (derate is not OCV)." Third place was awarded to Paul Zimmer of Zimmer Design Systems for "'There's a better way to do it!' - Simple DC/PT Tricks That Can Change Your Life." [ more ]

Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY
Synopsys announced availability of the DesignWare® DDR multiPHY which is designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. These standards include LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L (1.35 V), DDR3U (1.2x V), and DDR2. The DesignWare DDR multiPHY enables designers to target different DDR types for a single chip through simple software control. This capability makes it extremely flexible to integrate into an extensive array of applications such as consumer electronics, mobile, networking, server, computing, commercial/industrial and automotive applications. The DesignWare DDR multiPHY supports data rates from 0 to 1066 Mbps and offers a DFI 2.1 compliant interface to the memory controller. [ more ]

SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family
Synopsys announced that SiliconBlue has chosen Synopsys Synplify Pro® FPGA synthesis software as the synthesis tool of choice for its iCE65™ family of mobileFPGA™ devices. SiliconBlue will distribute with its iCEcube™ software a version of the Synplify Pro software optimized for iCE65 devices. This version of the Synplify Pro software will have a thorough understanding of the unique architectural structure of SiliconBlue's devices, bringing Synopsys' world-class synthesis and mapping technology to SiliconBlue customers. [ more ]

Synopsys Galaxy Implementation Platform Enables First-pass Silicon Success on Infineon's 40-nanometer X-GOLD 626 Wireless Product
Synopsys announced that the Galaxy™ Implementation Platform has helped Infineon Technologies AG (NYSE: IFX) achieve first-pass silicon success of the 40-nanometer (nm) baseband processor for its X-GOLD™ 626 3G wireless analog and digital system-in-package (SIP). Infineon utilized the Galaxy platform's powerful implementation flow to optimize the chip's multiple functional modes with multi-corner/multi-mode (MCMM) technology, taking advantage of the links between Synopsys' Design Compiler® RTL synthesis solution and IC Compiler placement and routing. The Galaxy platform's extensive support for low power and hierarchical design techniques, coupled with its signoff capabilities, was essential to achieve Infineon's tight schedule and high-performance, low power and area goals. As a result, Infineon met its design targets and taped out the baseband processor for the X-GOLD 626 wireless product ahead of schedule. [ more ]

Design Compiler 2010 Doubles Productivity of Synthesis and Place and Route
Synopsys introduced Design Compiler® 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a twofold speedup in the synthesis and physical implementation flow. To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce "physical guidance" to Synopsys' flagship place-and-route solution, IC Compiler, tightening timing and area correlation to 5 percent while speeding up IC Compiler's placement phase by 1.5 times (1.5X). A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Additionally, Design Compiler's new scalable infrastructure tuned for multicore processors yields 2X faster synthesis runtimes on four cores. These new Design Compiler 2010 productivity improvements will be highlighted today by users at the Synopsys Users Group (SNUG) meeting in San Jose, California. [ more ]

Synopsys Completes Acquisition of CoWare, Inc.
Synopsys announced it has completed its acquisition of CoWare, Inc., a global supplier of software and services for electronic systems design.

With embedded software becoming more pervasive, system-level design and verification solutions are gaining traction among developers. The addition of CoWare's talent and complementary technology extends Synopsys' activities in the system-level design market segment. Synopsys will be able to accelerate and bring to market new solutions based on open interoperability standards so engineers can more quickly design processor and software-intensive products. [ more ]

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