Synopsys' SystemVerilog Catalyst program promotes the development and use of EDA tools, verification IP and training services supporting the SystemVerilog standard for design and verification.

Corporate members of the SystemVerilog Catalyst Program may gain access to Synopsys' design and verification tools including VCS™, HDL Compiler™, the front-end language compiler for Design Complier™, and LEDA® for the purposes of developing SystemVerilog-based tools, ensuring their interoperability and providing support for mutual customers.