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Overview
The Synopsys DesignWare® DDR2/3-Lite SDRAM Memory Controller IP (MCTL) offers an efficient digital interface between up to 32 on-chip application buses and a DDR2/3-Lite physical layer (PHY) in a DDR3 or DDR2 memory subsystem. The DesignWare Memory Controller is a full-featured memory controller that provides efficient DDR control and protocol translation, support for multiple application ports, quality of service (QoS) control and optimized memory transaction scheduling. The MCTL also handles all initialization tasks for the memory subsystem including DRAM initialization and PHY data training. Used together with the DesignWare DDR2/3-Lite PHY IP, and Verification IP, the DesignWare DDR Cores are the low risk, highest performance, and the only complete, fully validated DDR2/3 IP solution in the market.
The DDR2/3-Lite MCTL is compatible with all DesignWare DDR2/3-Lite PHY IP.
Highlights
- Supports JEDEC-standard DDR3 and DDR2 protocols (JESD79-3 and JESD79-2, respectively)
- Provides a complete, single vendor DDR3/DR2/SDRAM interface IP solution, when combined with the DesignWare DDR2/3-Lite PHY IP
- Contains basic data training logic for supporting DesignWare DDR2/3-Lite PHYs
- Configurable multi-port arbiter with up to 32 independent user ports
- Each user port can be a generic synchronous interface or AXI
- Supports x8, and x16 memories
- Supports memory interfaces of 8 to 64 bits in 8 bit increments (up to 72 bits with ECC)
- Supports 1 to 4 memory ranks
- Provides advanced command re-ordering and scheduling to maximize memory bus utilization
- Command reordering between banks based on bank status
- Enables automatic scheduling of activate and precharge commands
- Enables automatic scheduling of refreshes
- Configurable per-command priority with up to 8 priority levels
- Programmable ECC generation, checking, and correction
- 2:1 architecture (width ratio of 2:1 from application bus to memory data bus) with maximum 533 MHz clock speed for up to 1066Mbps
- Configurable and programmable address mapping
- Programmable for different SDRAMs, and also programmable for mapping of rank, bank, row, column
- Supports gDDR2 SDRAMs
- DDR3 write leveling is not supported in DesignWare DDR2/3-Lite products
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