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Overview
Synopsys DesignWare® DDR3/2 PHY Cores are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM Memories. The DDR3/2 PHY IP supports the entire range of DDR3 SDRAM speeds, from DDR3-800 through DDR3-1600, with backward compatibility provided for DDR2-667 through DDR2-1066 devices.
The DesignWare DDR3/2 PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR3/2 PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a single Address/Command macro block and multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width.
A key component of the DesignWare DDR3/2 PHY is the extensive in system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DesignWare DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.
The SSTL_15/_18 I/Os provide fully JEDEC compliant signaling and feature PVT compensated, programmable drive strength, PVT compensated on-die termination (ODT) and IDDq test mode with LVCMOS input capability.
DesignWare DDR3/2 SDRAM PHYs are compatible with the DesignWare DDR3/2 Protocol Controller IP and the DDR3/2 Memory Controller IP.
Highlights
- When combined with a DesignWare DDR3/2 digital controller core and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
- Scalable architecture that supports the speed range, from DDR2-667 up to DDR3-1600
- Delivery of product as a hardened Mixed-Signal macrocell components allows precise control of timing critical delay and skew paths
- Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
- Support for 1 to 4 memory ranks
- DDR3/2 PHY-Controller interface runs at either 2:1 or 4:1 mode (width ratio of application bus to memory data bus), simplifying core logic timing constraints
- Includes the PLL and all timing circuits necessary to meet timing specifications
- Write leveling timing circuits to compensate address and control versus data delays
- Write and read bit timing circuits compensate per-bit delay skew of individual data bits within each data byte
- Locally calibrated master and slave timing circuits minimize OCV and ACLV effects, and accommodate V, T timing drift
- Read and Write data eye training and bit level deskew support through APB register interface
- Functionality for data training resides with DesignWare DDR3/2 digital controller cores
- Area optimized I/O: 35um I/O pitch
- Application specific DDR3/2 I/O library featuring PVT independent ZQ/RZQ programmable ODT and drive strength
- Includes RTL controller logic for calibration
- Includes power, spacer, and corner cells
- Supports CUP (Circuit Under Pad)
- At-speed internal loopback testing
- 1149.1 JTAG Boundary Scan
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