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Overview
The DesignWare® Switch Bridge Port (SW/BP) PCI Express™ Core is configurable and scalable to meet multiple switch port application requirements.
The enhanced capabilities of the DesignWare SW/BP core allow for optimal on-chip memory size and utilization, significant power savings and low latency.
The core implements most advanced capabilities of PCI Express such as active state power management, advanced error reporting, multiple virtual channels, and End-to-End CRC.
The application interface directly supports multiple clients and offers maximum flexibility for end-use applications.
The synthesizable core integrates quickly and easily into SoC designs with a user-friendly application interface and conservative timing suitable for a wide range of ASIC and FPGA technologies.
The core is available in your choice of datapath widths, PIPE interface widths, and operating frequencies for optimization of size, power, and throughput.
DesignWare PCI Express cores are fully compliant with the PCI Express Base Specification 1.1/2.0 and are used to power the industry's PCI Express compliance testing at PCI-SIG Compliance Workshops.
Applications
The DesignWare Switch core supports a wide variety of PCI Express 1.1/2.0 applications:
- PCI Express to PCI/PCI-X bridge
- PCI/PCI-X to PCI Express bridge
- Hyper-transport to PCI Express bridge
- SATA to PCI Express bridge
- Transparent PCI Express switch
- Non-transparent PCI Express switch
Highlights
- Compliant with PCI Express 1.1/2.0 Specifications
- Modular Design: base CXPL core with additional support modules
- Architecture supports x1, x2, x4, x8, x16, 2.5/5.0 Gbps lane configurations
- Available in 32, 64, or 128 bit datapath widths
- 125MHz/250MHz/500MHz operation
- Type 1 configuration space register support
- Supports PIPE PHY 1.86 interface definition including variable clock and variable data
- Configurable upstream and downstream port
- Ultra low transmit and receive latency
- Configurable retry buffer size
- Bypass, cut-through, and store/forward configurable transmit and receive queue
- Configurable multi/single transmit and receive queue structure
- Pre-fetch memory space support
- Transaction filtering and routing look up
- Full PCI bridge-to-bridge support
- Configurable VC/TC mapping
- Lane reversal and polarity inversion (TX/RX)
- Configurable multi-VCs/multi traffic class support
- Packet sizes: configurable maximum payload size (128B to 4KB) and Max request size up to 4KB
- Complete Switch Port (upstream or downstream) link training (LTSSM)
- Full PCI-PM software and ASPM support
- Full Advanced PCI Express Error Reporting
- Full PCI Express message forwarding and processing
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