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Overview
The Synopsys DesignWare® Hi-Speed USB 2.0 On-The-Go (HS OTG) PHY is a complete mixed-signal semiconductor intellectual property (IP) solution,
designed for single-chip, USB 2.0 integration in OTG applications. The USB 2.0 OTG PHY includes all the required logical, geometric,
and physical design files to implement USB 2.0 Hi-Speed OTG capability in a system-on-chip (SoC) design and to manufacture it in the designated foundry.
The USB 2.0 OTG PHY is available in 90-nanometer (nm), 0.13-micron, and 0.18-micron CMOS digital logic processes.
Alternatively, design services are available for porting the USB 2.0 OTG PHY to other semiconductor processes.
The DesignWare Hi-Speed USB 2.0 OTG PHY integrates high-speed, mixed-signal, custom CMOS circuitry designed to the UTMI+ Level 3 Specification.
The PHY supports the USB 2.0 480-Mbps protocol and data rate (hi-speed), and is backward compatible to the USB 1.1 legacy protocol at 1.5-Mbps (low-speed) and 12-Mbps (full-speed).
The flexible architecture of the PHY enables it to be connected with a HS OTG subsystem to perform as a standard Hi-Speed, Dual-Role Device (DRD),
operating as either a fully USB 2.0 Hi-Speed compliant peripheral or an OTG host. For example, when the USB 2.0 OTG PHY is implemented in a USB printer, the printer can print from a PC,
or the printer can act as the host, extracting and printing pictures directly from the memory of a digital camera without the aid of a PC.
Additional applications include PDAs, mobile phones, MP3 players, set-top boxes, scanners, and fax machines.
Highlights
- Complete mixed-signal physical layer (PHY) for single-chip USB 2.0 OTG applications
- USB 2.0 Transceiver Macrocell Interface (UTMI+ Level 3) Specification
- USB 2.0 Device automatic switching between full- and high-speed modes
- Host Device automatic switching between full-, high- and low-speed modes
- 8-bit interface at 60-MHz operation and 16-bit interface at 30-MHz operation chip
- Designed for rapid integration with Synopsys' USB 2.0 On-The-Go controller
- Designed for minimal power dissipation for low-power and bus-powered devices
- Low-power design enables host enumeration of an unpowered device
- Sea-wall and decoupling structures reduce on-chip noise
- Suspend, Resume and Remote Wakeup mode support
- USB 2.0 test mode support
- Additional built-in analog testability features
- Based on Synopsys' USB Implementers Forum certified High Speed USB 2.0 PHY architecture
Interested in learning more about the USB 2.0 PHY? Download the actual USB 2 PHY model for a specific process and configuration.
Run some simulations and see how Synopsys' Hi-Speed Certified USB 2.0 PHYs can meet your SoC design needs. To request the evaluation package,
please go to Try-the-PHY.
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