Welcome to the DesignWare Technical Bulletin This quarterly newsletter brings you up-to-date on recent DesignWare IP news, from product announcements to upcoming seminars.
PCI Express Switch Enumeration Using VMM-Based DesignWare Verification IP
PCI Express utilizes a point to point interconnect and implements switches to expand the number of PCIe connections in a system.
The Switch enumeration process is used to discover the available devices in the PCI tree so they can be allocated by the system software.
paper explains how designers can use the VMM-based DesignWare Verification IP for PCI Express with support for SystemVerilog to perform
the configuration task during the Switch enumeration process.
USB 2.0 IP with Link Power Management Extension
Learn about the USB 2.0 Link Power Management (LPM) specification and how it can lower power in your SoC designs.
Discover the various states and benefits of LPM and see how the LPM protocol extension and functions impact your design.
Functional Coverage Techniques: Leveraging DesignWare Verification IP and VMM for Efficient Testbenches
Today's large and complex designs have created the need for new approaches to verification.
For maximum efficiency, a combination of unified technologies offers the best gains.
The Verification Methodology Manual for SystemVerilog used with Synopsys® DesignWare® Verification IP (VIP) is such a combination.
This article touches on how to leverage the benefits of each to achieve functional coverage goals with a constrained random methodology.
Virtualize Your Connectivity IP with DesignWare System-Level Library
Building on the success of Synopsys' leading connectivity IP portfolio of popular protocols,
the DesignWare® System-Level Library mirrors the availability of implementation blocks at the system-level to allow efficient re-use in virtual platforms for pre-silicon embedded software development.
Learn how the coordinated availability of IP at the system-level makes it easy to develop, analyze and deploy virtual platforms which use Synopsys IP.
FEATURED WHITEPAPERS
Using Virtual Platforms for Pre-Silicon Software Development
Recent market research indicates that today - in 2008- the development effort for software running on 90nm and below has already surpassed the effort for the hardware development.
The projection for 2011 is that less than 40% of the chip development cost is spent on hardware.
It is the software which dominates and has become the bottleneck.
This white paper provides an overview of the topic of using virtual platforms for pre-silicon software development.
The paper describes an example of several virtual platforms and the different use models.
Implementing Physical Layer Connectivity IP in Deep Sub-Micron Technologies
After an introduction to circuit and process trends in deep sub-micron technologies, this article will present a complete protocol solution using the high speed memory DDR2 interface as an example.
This is followed by a description of the implementation challenges of integrating IP into a SoC.
The article concludes with a proposal for production testing of high-speed serial PHYs.
TRAINING AND EVENTS
Free Technical Webinar
Building a VMM-Based Constrained Random Environment for Bus Protocol Verification
July 15, 2008 - 11:00 a.m. PT Register Now
On-Demand Webinar
Selecting the Optimal Embedded Memory IP Architecture View Now
