DesignWare® Embedded Memory IP

Content and feature-rich products require faster, more power efficient SoCs with increasingly large amounts of on-chip memory. With memory consuming over 50% of the chip area and clock speeds increasing at 25% yearly - memory, power, area and performance are critical contributors to the overall design viability.

The DesignWare® embedded memory IP offering includes an innovativeSRAM-1T IP that is implemented in bulk logic CMOS, requiring no additional manufacturing steps and a set of low power, high performance standard SRAMs. Unlike competitive solutions, the compiler-based solution provides designers with immediate access to the specific memory instance which is needed without compromising on instance size or topology. The DesignWare embedded memory is ideal for very high density memory integration of ASICs, ASSPs, SoCs and System-in-Package applications.

DesignWare coolSRAM-1T™ IP
Cost Effective 1 Transistor SRAM

• Up to 3x more dense than SRAM-6T
• For chips containing over 50% of embedded memory, it saves up to 20% in die area
• Bulk logic CMOS process
  • Requires no additional manufacturing steps
  • Reduces wafer manufacturing costs by up to 15% compared to other SRAM-1T products

• Includes single port, dual port, register file and high density ROM
• Enables implementation of 32Kb cache, at over 1.2GHz designs on 65nm low power process
• Reduces dynamic power consumption by up to 50% with advanced power management features such as the ability to power down portions of a memory instance when not in use
• Supports individual bit writes, thus reducing power consumption

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