DesignWare® Mixed Signal IP Solutions

Today's complex designs are quickly transitioning to high-speed interconnect standards, which are performing well into the gigahertz range. Synopsys' comprehensive portfolio of high-performance mixed-signal PHY IP for the PCI Express®, SATA, XAUI and USB protocols enables designers to quickly integrate high-performance interfaces into their next-generation SoCs.

The DesignWare PHYs are based on an advanced analog architecture designed to scale to the next generation of data rates and process technologies as new high-speed SERDES protocols evolve. To meet the needs of the networking, storage, computing, and consumer electronics markets, all are available in leading 130- and 90-nanometer (nm) process technologies.

With Synopsys' years of technical experience in developing high-speed SERDES technology, designers can have confidence that the IP is built with the highest quality standards. This combined with our comprehensive worldwide technical support will be there to support you from concept to silicon.

• Complete solution with PHY, digital controller, & verification IP
• High performance architecture provides low area and up to half the power consumption of other solutions in the market today
• Very low jitter and excellent receive-side sensitivity for the lowest Bit Error Rate (BER)
• Advanced built-in diagnostics and test capabilities in the PCIe, SATA and XAUI PHYs enable fast and efficient debug during production and manufacturing

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