RTL Synthesis Archives

Press Releases

• Synopsys Design Compiler Topographical Technology Adopted by IBM to Accelerate ASIC Designs
• Synopsys Design Compiler 2007 Boosts Designer Productivity and IC Performance
• Synopsys Enables STMicroelectronics to Achieve First-Silicon Success for 65-nm
• STARC Deploys Synopsys Design Compiler Topographical Technology in New 65nm Methodology
• Synopsys Design Compiler Topographical Technology Expedites ASIC Design at STMicroelectronics
• Synopsys Design Compiler Topographical Technology Accelerates Tapeout of 90nm Multimedia Chip at ETRI
• Displaytech Switches to Synopsys Design Compiler Tool for Next-Generation FLCOS Microdisplays
• Progate Adopts Design Compiler Topographical Technology for Faster Time-to-Results
• Galaxy Platform Reduces Power Consumption of Industry-Leading Multi-Voltage Designs
• Design Compiler Topographical Technology-Based ARM-Synopsys Reference Methodology Delivers Higher Productivity
• DFT MAX Cuts Test Cost on Nanometer Designs
• SGI Adopts Synopsys Design Compiler Topographical Technology for Predictable RTL-to-GDSII Flow
• NVIDIA Adopts Synopsys Design Compiler Topographical Technology
• DFT MAX Cuts Test Time and Cost on CSR Bluetooth Design

Articles

• Test and Measurement World: ITC: Synopsys addresses yield, memory test, and small delay defects
• EE Times Asia: Flexible Analysis is Key to Power Integrity
• EE Times Asia: Achieve Low-Power Design Success at 65nm
• EE Times: Power integrity analysis for billion-transistor full-custom designs
• EE Times: Synopsys donates technology to Accellera low-power effort
• EE Times: Accellera Rolls Power Plan
• Test & Measurement: Limits of Test Time Reduction
• EE Times: How Much Test Compression is Enough?
• EE Times: Critical Area Optimizations Improve IC Yields