Star-SimXT True-Hspice Full-Chip Simulation

Overview
Star-SimXT™ is the only high-capacity circuit simulator that handles circuits with billions of elements, handles them 10,000 times faster than SPICE, yet also provides 0% error compared to HSPICE®. Star-SimXT provides an order-of magnitude improvement in productivity over Star-Sim for post-layout analyses including timing, power, rail, clock and crosstalk. True-Hspice™ is a critical enabling technology for Star-SimXT. By unifying Star-SimXT and HSPICE capabilities, True-Hspice allows the use of foundry-validated models in Star-SimXT. The Dynamic-Hierarchy™ engine is a second enabling technology in Star-SimXT. It provides the capacity and speed benefits of hierarchical simulation without sacrificing accuracy or speed for non-hierarchical or post-layout simulations.

Star-SimXT Benefits

• True-Hspice accuracy for full-chip simulation delivers 0% modeling error with validated-to-silicon foundry sign-off.
• Complete post-layout analysis solution for timing, power, rail, and crosstalk including fully coupled RLC parasitics.
• Based on production proven technology with over 1,000,000 customer design simulations.
• Highest capacity.over 1 billion elements.of any circuit simulator.
• Push-button verification within the SinglePass-Soc flow for critical nets such as clock nets.
• Accurate power analysis of full-chip designs replaces inaccurate estimates based on static analysis or switching rate methods.
• Accurate analysis of power-rail effects such as IR drop and ground bounce including all parasitic RLC effects.

Figure 1: Integrated environment for clock-tree analysis.

Overview
Successful IC design engineers deliver high-performance, high-yield silicon on time. But decreasing design cycle times and the emergence of new physical effects (at 0.10 micron and below) render previously successful design methodologies obsolete. In all areas - capacity, accuracy, speed and productivity - new solutions are required that are an order-of-magnitude better than existing commercial simulation tools.

Star-SimXT delivers the required solutions. Raw engine performance, a necessary condition for designer productivity, is increased an order of magnitude over Star-Sim performance. Further, flow productivity for timing, power, crosstalk and rail analyses is also increased by an order of magnitude.

Star-SimXT Features:

• Dynamic transistor circuit simulation using device models.
• Simulation capacity of one billion circuit elements, without macro or behavioral modeling.
• Verilog VCD support for input vector and expected output signal checks.
• Built-in diagnostics including rise, fall, setup and hold times, current surge and IR drop detection.
• Interactive workbench for customized simulation control and debugging.
• Cosmos-Scope™ included for complete waveform analysis via patented waveform calculator.

True-Hspice™ Technology Matches Foundry Silicon
For sensitive analog or high-speed digital circuitry, Star-SimXT employs True-Hspice technology to exactly match HSPICE in accuracy. Star-SimXT shares HSPICE's foundry-validated device models and simulation algorithms through True-Hspice, the new architecture that unifies Star-SimXT and HSPICE to ensure silicon accuracy. True-Hspice base technology is production proven with over 1,000,000 customer simulations and is endorsed and used at every major foundry worldwide.

Guaranteed silicon accuracy is the foremost requirement for any circuit simulation tool. Star-SimXT is the only full-chip circuit simulator that directly uses HSPICE device models and algorithms. True-Hspice accuracy is vital for designs at ultra-deep-submicron (0.10 micron) and below, where inaccuracies in device modeling from traditional 'table-model' based simulators is unacceptable.

True-Hspice has low computational overhead and is necessary for analog, high-speed digital, and charge-sensitive circuits where device modeling accuracy is extremely important.

True-Hspice models ensure silicon-accuracy by exactly matching HSPICE results.

Dynamic Hierarchy Engine
Limitations of full-chip static timing analysis techniques, as well as increasing design sizes, have increased the performance demands on circuit simulation tools. Hierarchical circuit simulation is the process by which hierarchy.either explicit or implicit in the netlist.is leveraged to reduce memory usage and increase simulation performance.

Star-SimXT's Dynamic-Hierarchy architecture is the first to combine the production-proven accuracy of HSPICE with the capacity and speed of hierarchical circuit simulation. Up to one billion circuit elements (on a common server workstation) can be simulated at speeds 10 times faster than previously possible.

Star-SimXT's Dynamic-Hierarchy engine is the second generation of industry's first hierarchical circuit simulator. Hierarchy within the design is leveraged to optimize memory and runtime performance, with the dynamic activity of the circuit determining the computational activity at any given time. Such optimization is similar to the caching and pipelining techniques used in microprocessor design; indeed, Star-SimXT's unique multi-threading capability is enabled by this novel dynamic-hierarchy architecture.

The Dynamic-Hierarchy engine provides advanced features not found in traditional circuit simulators. Key architectural benefits are:

• Explicit or implicit design hierarchy enables one billion circuit element capacity on modern server workstations.
• The simulated circuit's dynamic activity determines partitioning and latency during simulation, thereby providing a 10X improvement over non-dynamic architectures.
• Integral multi-threaded kernel enables up to 3X speed increase.
• Back-annotated parasitics, flattened for post-layout accuracy, do not adversely affect runtime or memory efficiency.
• Non-ideal internal power-rails, or power-rail parasitics, are simulated while not strongly affecting engine performance or memory usage.

Post-Layout Analysis
Star-SimXT's architecture transcends the limitations of all other point-tool simulators via direct integration with Star-RCXT™for parasitic extraction. Together with Star-RCXT, Star-SimXT provides the most efficient solution for post-layout analysis of high-performance blocks or critical paths. Critical post-layout effects such as ground bounce, voltage drop, clock skew, signal crosstalk and power analysis require a tightly integrated extraction and simulation solution, based on Star-SimXT and Star-RCXT. By using a pro-prietary Active-Parasitics™ technology, they dynamically communicate to minimize memory usage and runtime, while avoiding the sacrifice in accuracy of so-called "hierarchical extraction flows."

Enabling technologies are:

• The Active-Parasitics link between Star-RCXT and Star-SimXT reduces overall memory and runtime by 10X for circuits with high latency.
• Built-in parasitic reduction in Star-SimXT complements the reduction in Star-RCXT. Star-SimXT's reduction speeds runtimes even further, up to 10X, while preserving accuracy and guaranteeing circuit passivity, even on circuits with parasitic inductance and coupling capacitance.
• Parasitics on power rails or internal power supplies (charge pumps) are handled automatically without adversely affecting engine speed or capacity.

Formats and Models

• Input formats: HSPICE, SPICE, VCD, DSPF
• Output formats: GSI(.tr0), XP, NW, WDB, VCD

Platforms and Operating Systems

• Sun: Solaris 2.5, 2.7(64-bit and 32-bit)
• HP: HPUX 10, 11 (64-bit and 32-bit)
• IBM: AIX 4.3 (64-bit and 32-bit)

Recommended Hardware Configuration

• RAM: 256MB
• Disk: 2GB
• Swap: 500MB

For more information about Synopsys products, support services or training, visit us on the web at www.synopsys.com, contact your local sales representative or call 650.584.5000.