Key Benefits

• High performance and high capacity simulation, advanced testbench automation, assertion verification, coverage analysis and SystemVerilog support in a single product
• Most effective solution to find more bugs in less time
• Based on industry standards to secure your verification investments

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DAC 2008: VMM User Forum Methodology Beyond Base Classes ARM, IBM, Nortel, NVIDIA, and Renesas explore the current state of the art in verification methodologies ,discuss how methodology is expanding beyond simple base class libraries and share real-life experiences with VMM.

Design Challenges
An increase in RTL design size and complexity creates an exponential growth in verification challenges. This growth, coupled with Moore’s law for design size, requires advanced technologies and methodologies to ensure the highest design quality.

Solution
Synopsys offers the best-in-class technologies and methodology to enable thorough verification of RT Level designs, quickly. Synopsys’ Smart RTL verification enables a design-for-verification (DFV) methodology that allows engineers to specify design intent using assertions and interfaces upstream in the design process. This enables highly effective dynamic and static verification. For example, when using this methodology engineers write assertions once, then use them for formal property verification, dynamic simulation including protocol checking, testbench reactivity and coverage analysis. DFV methodology ensures designs are verification ready, resulting in early and systematic detection of bugs. Synopsys enables DFV methodology by providing a powerful set of products for RTL verification in a unified integrated platform.

VCS provides the high performance and capacity simulation required to verify today’s multi-million gate designs and uniquely raises verification efficiency by supporting the design-for-verification (DFV) methodology. Full-featured, Native Testbench support for SystemVerilog and OpenVera® testbenches enables the creation of highly effective verification environments using object-oriented techniques, constrained-random stimulus and functional coverage, and provides up to 5X faster verification performance compared with stand-alone testbench tools. Native technology for assertions, testbench and coverage in VCS enables higher productivity, performance and quality, resulting in higher confidence in verification results as well as reducing the verification process.

Pioneer-NTB is a full-featured SystemVerilog testbench automation tool for use with popular VHDL and Verilog simulators. Pioneer-NTB enables engineers to easily adopt advanced verification methodologies using open standards in mixed-simulation environments. Pioneer-NTB is built on the powerful, production-proven technologies of Synopsys’ VCS comprehensive RTL verification solution and Vera® testbench automation tool, and provides instant access to the extensive VCS and Vera ecosystems. Pioneer-NTB also supports the OpenVera language, enabling existing Vera verification environments to be easily migrated to Pioneer-NTB for up to 2x faster verification runtime performance.

The VCS Verification Library provides the industry’s broadest portfolio of verification IP for today’s most popular bus and I/O standards. It also includes Design Views for DesignWare Star IP processor cores and thousands of memory models. The VCS Verification Library offers extensive support for the Synopsys Reference Verification Methodology (RVM) and gives engineers up to 5X improvement in runtime performance when used with Synopsys VCS RTL solution. The verification IP in the library integrates easily into Verilog, SystemVerilog and OpenVera testbenches to generate bus traffic, insert error conditions, and check for protocol violations. The Monitors provide extensive reports to show functional coverage of the bus protocols.

Magellan is a hybrid RTL formal verification product that allows engineers to find deep, corner-case bugs, quickly, resulting in a shortened functional verification cycle and higher quality designs. Magellan’s unique hybrid architecture combines the strengths of new, advanced formal engines with the strengths of a built-in VCS simulation engine to verify properties and assertions on large and complex designs.

Assertions provide a way to concisely describe intended design behavior and are usable across dynamic and formal verification environments. With assertions, verification engineers can increase productivity and the ability to find design bugs by writing less code to check assertions on their designs. Assertions are supported across Synopsys verification products to ensure their most effective use of finding bugs quickly and easily.

Vera, an advanced testbench automation tool, addresses the challenge of improving verification productivity. Vera significantly improves verification quality by enabling the creation of sophisticated test scenarios to help identify hard to find bugs.

Leda analyzes a design’s RTL and identifies code as well as design related bugs. For example when multiple clocks at different frequencies are used in the design, Leda can check if clock domain crossing is happening correctly or if it will result in a bug in the design. Leda checks designs for conformance to low-power/multi-voltage rules, checks SDC constraints for correctness, and verifies constrains against designs. Leda also analyzes designs to check if the implementation will result in the best QoR for Design Compiler or if the design will deliver the best performance for the VCS simulator.

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