TCAD Sentaurus Lithography (S-Litho)
Sentaurus Lithography provides the most accurate models for simulating microlithography processes and techniques in three dimensions, supporting development and optimization tasks for the most advanced nodes in integrated device manufacturing. S-Litho addresses the modeling of state-of-the-art lithography simulation tasks, and determines resulting resist profiles using a physical and highly predictive resist model.

Sentaurus Lithography (S-Litho) models all of the processes and techniques involved in microlithography. It can simulate the evolution of three-dimensional topographic features in integrated circuit devices throughout the various phases of the microlithography process. Due to its sound physical approach, S-Litho has a high predictive power, enabling lithography engineers to draw on simulation results to develop and optimize process technologies.

S-Litho sets a standard in lithography simulation, addressing the challenges found in current and future process technology nodes. It provides a powerful analysis tool to simulate rigorously the outcome associated with the most advanced resolution enhancement techniques. All features of S-Litho are embedded in an intuitive graphical user interface, which allows engineers to navigate easily through a wide range of lithography simulation capabilities.

The combination of S-Litho and other members of the TCAD Sentaurus product family allow customers to optimize the entire wafer process cycle. This helps to shorten process development time, increase yield and fully exploit the capabilities of existing equipment. The combination of S-Litho with Synopsys’ OPC tools (e.g. Progen) will support faster generation of more accurate OPC models.

Benefits

• Enable fast and effective lithography process development and optimization for current and future technology nodes, reducing development and production ramp time
• Support the optimization of process robustness and stability by providing tools for the rigorous simulation, fast and accurate algorithms, and physical resist models
• Enable the optimization of design structures and the verification of mask layouts, improving yield
• Improve flexibility during volume manufacturing by adjusting lithography conditions to wafer stack or mask variances