Overview
Process variations will increasingly impact circuit performance from 65 nm onwards due to feature scaling and the use of process steps like strain engineering. Unlike litho (OPC/RET) effects, currently, strain engineering has no knob to turn for compensation of layout dependency. Excessive guard bands with restrictive design rules can be overly pessimistic, resulting in sacrificing performance.

To account for transistor variability impact on parametric yield, designers need tools that accurately model the different sources of variations and make appropriate changes to the design. The Synopsys process-aware design for manufacturing (PA-DFM) product family’s core products – Seismos and Paramos – link manufacturing variation information back to design, enabling custom (IP, cell, memory and analog) designers to optimize layouts and maximize yields.

Seismos and Paramos address two major sources of variability in a design:

• Proximity variations due to stress and other proximity effects
• Global variations due to the spread of manufacturing process parameters across different die and wafers

Building on Synopsys’ TCAD expertise in advanced process and device modeling, the PA-DFM products allow custom designers to account for manufacturing variability without major changes to the current physical design flow. To help ensure seamless integration with the existing design infrastructure, the PA-DFM products are built to easily "drop in" to customers’ existing custom design flow and methodology, protecting their investment while fulfilling a critical need for reduced variability and increased circuit performance.

Together with the company's industry-standard HSPICE® circuit simulation tool, PrimeTime® VX, and Star-RCXT™ VX tools, the PA-DFM product family underscores Synopsys’ focus on optimizing variation awareness for increased performance, productivity and predictability. All of these tools are highly complementary, providing customers with comprehensive modeling capabilities of variability issues from cell layout through design implementation.

Benefits

• Links manufacturing variation information back to design, enabling custom designers to optimize layouts
• Allows custom designers to realize the full potential of technology scaling and, in turn, expand the latitude for yield maximization

Value

• Enhances design PREDICTABILITY by
1. Minimizing unknown process variations
2. Providing variability analysis capability to reduce chip respins
• Increases design PRODUCTIVITY by
1. Enabling interactive “what-if” analysis to explore and optimize design layout
2. Providing an evolutionary approach to account for variability within existing design infrastructure
• Boosts chip PERFORMANCE by
1. Reducing unnecessary guard-bands
2. Optimizing design layout to realize the full potential of technology scaling