Vera Testbench Automation

Overview
Vera® is an industry-leading testbench automation product that increases design quality by finding simple as well as corner-case bugs, quickly. Vera allows engineers to create coverage-driven tests using advanced testbench concepts like constrained-random stimulus generation, real-time data and temporal checking and extensive analysis of functional coverage. Vera combines next-generation constraint solving and coverage analysis engines with a proven reference verification methodolgy and interfaces to leading Verilog and VHDL simulators. Vera supports the OpenVera® hardware verification language, including OpenVera Assertions, and is an integral part of the Synopsys Discovery™ Verification Platform.

Highlights

• Very easy to learn, deploy and use across big or small projects
• Customer-proven reference methodology speeds deployment of reusable verification environments
• Next-generation constraint solver rapidly generates complex tests
• Powerful functional coverage analysis provides detailed feedback
• Real-time data and temporal checking enable reactive testbenches
• Supports all leading Verilog, VHDL and mixed-language simulators
• Accelerates verification ramp up with DesignWare® Verification IP
• Integral part of Synopsys Discovery Verification Platform

Figure 1. Vera enables higher verification productivity with advanced language features

Figure 2. Vera finds more bugs with constrainedrandom, coverage-driven test

Figure 3. Vera's layered teshbench architecture enables efficient, reusable verification environments

Finding Bugs Faster
Vera combines advanced language features, powerful verification engines, and a customer-proven methodology to enable the early identification of design bugs.

Constraint-Driven Test Generation
Vera's next-generation constraint solver is flexible and powerful, enabling users to implement a highly efficient constrained-random verification methodology. The solver uses formal techniques and multiple engines to provide unprecedented power to solve highly complex constraint sets. Users can quickly get solutions for thousands of simultaneous constraints, each with hundreds of random variables. The advanced solver enables users to thoroughly simulate a design's functionality, including corner-case scenarios, resulting in greater confidence in the design quality.

Functional Coverage Analysis
Functional coverage analysis provides a measure for the quality of a constrained-random verification methodology. Vera provides a powerful functional coverage engine that supports test grading, coverage accumulation across regressions and HTML-based coverage reporting. The functional coverage engine is integrated with the stimulus generation engine to support reactive test generation to eliminate redundancy in the regression suite.

Data and Temporal Checking
OpenVera Assertions (OVA) give users an easy to use way to capture descriptions of the design behavior. Vera supports OVA to offer maximum flexibility in the development of protocol checkers and monitors. Additionally, OpenVera testbenches react to assertion conditions, enabling development of a reactive testbench. OVA can be used across the complete verification flow from simulation to testbenches to coverage to formal analysis.

Reference Verification Methodology
Vera's powerful testbench engines are complemented by a proven reference verification methodology and layered testbench architecture that enables both new and experienced verification engineers to quickly create and deploy advanced, reusable, efficient verification environments. This methodology, developed and used by verification experts, helps users adopt industry best practices to get the best possible results from Vera. A detailed reference manual, pre-written testbench building blocks (base class library) and examples are provided with Vera.

Aspect-oriented Extensions to Object-Oriented Programming
Vera's object-oriented programming model is enhanced with aspect-oriented extensions to provide increased testbench-coding productivity. Object-oriented programming is essential to create a well-structured testbench foundation that is easy to maintain. The addition of aspect-oriented extensions helps engineers to quickly and easily create individual tests built on this testbench foundation, thus improving test-writing productivity.

Transaction-Level Interface to SystemC
Many designers create reference models in SystemC™ prior to coding RTL. Vera enables the use of a single, golden testbench to drive both SystemC and RTL representations of a design, ensuring consistency between the transaction-level model and the detailed implementation. Vera’s transaction-level interface to SystemC enables users to quickly and easily connect a Vera testbench to a SystemC model and then re-use the same testbench when RTL is available.

Figure 4. Vera's testbench debugger speeds development of verification environment

Figure 5. Discovery Verification Platform

Testbench Debugger
Vera provides a powerful and robust testbench debug GUI that helps speed creation and debug of advanced, multi-threaded testbenches. The Vera testbench debugger provides a complete environment for running and debugging testbenches, including the ability to set breakpoints, monitor variables, start/stop simulation, and much more.

DesignWare Verification Library
The DesignWare Verification Library, a subset of the Design- Ware Library, contains reusable, pre-verified verification IP of the industry’s most popular bus and I/O standards, AMBA verification solution, Design Views for Star IP processor cores and thousands of memory models. Written in OpenVera, DesignWare Verification IP takes advantage of constrained-random test generation techniques, dramatically improving the productivity of verification engineers and significantly reducing the risk of undiscovered functional bugs. Each DesignWare verification IP includes capabilities like automatic error checking, which helps verification engineers to quickly create more accurate, effective verification environments. In addition, customers can also elect to license single DesignWare verification IP suites out of the DesignWare Verification Library.

Discovery Verification Platform
The Discovery™ Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed signal, system-level verification, assertions, verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. The Discovery Verification Platform includes Synopsys’ VCS® complete RTL verification, System Studio for system-level verification, Leda® programmable RTL checker, Vera® testbench automation tool, Magellan™ hybrid RTL formal verification, DesignWare® verification IP, Formality® equivalence checker, NanoSim® and HSPICE® for mixed-signal simulation. Combined with SystemVerilog and Synopsys’ design-for-verification methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.