Post-Layout Flow Assistance Deploy an Optimized Post-Layout Methodology

Analog/mixed-signal (AMS) IC designs face significant implementation and verification challenges at deep sub-micron processes. Modeling accuracy and silicon prediction behavior is more difficult, and growing design complexities and process effects increase memory capacity requirements and simulation run times beyond the efficiency of traditional post-layout flows.

Synopsys Post-Layout Flow Assistance service helps you address common postlayout challenges by integrating Synopsys' Galaxy™ Implementation and Discovery™ Verification Platform features into your AMS verification flow. The resulting, reusable flow improves the modeling and simulation accuracy of your designs while reducing run-times and memory requirements.

Synopsys' highly-trained consultants combine an understanding of AMS design issues with extensive tool knowledge to deliver expert on-site services, transferring best-practices and advanced methodologies that help improve productivity and lower design costs.

Figure 1. Synopsys Post-Layout Flow.

• Synopsys specialists help deploy a reusable AMS flow with higher performance and better correlation to silicon
• Ensure detailed high-accuracy modeling of designs
• Optimize extraction and simulation processes to improve simulation run time and memory capacity requirements

Figure 2. Synopsys' integrated AMS sign-off solution supports advanced features such as multi-corner and hierarchical extraction, selective net extraction, and advanced dynamic and static power analysis.

The optimized flow consists of advanced parasitic extraction capabilities with Star-RCXT™ to ensure detailed, high-accuracy modeling for multi-corner, hierarchical, and selective net extractions. These features are complemented by Synopsys' HSIM® and NanoSim® high-speed simulators. With greater accuracy for evaluating process variation effects and other very deep submicron phenomena such as capacitive interaction, noise analysis, glitch detection, IR drop, and power consumption, silicon predictability and yield can be improved.

An industry leading wireless communication company was facing significant bottlenecks in its netlist back-annotation flow on a recent 65nm chip they were developing containing both digital and custom circuits. Large extraction files were impacting storage requirements, and lengthy IR drop simulations were taking days and sometimes weeks to complete.

Synopsys consultants worked with the design team to determine the bottlenecks in the current flow. To address the large extraction file size issue, the team implemented selective power net extraction in Star-RCXT and during simulation, and selective net back-annotation in HSIM power rail analysis and simulation. The Synopsys consultants also worked with the customer's engineers to optimize Star-RCXT and HSIM-PWRA for faster IP drop simulations. The improvements were significant. Extraction files were reduced by 4X and IR drop simulation times were reduced from eight days to less than one day while maintaining accuracy.

For more information about Synopsys' complete portfolio of consulting and design services, visit www.synopsys.com/sps

For more information about Galaxy tools and tool flows, visit: www.synopsys.com/products/solutions/galaxy_platform.html

For more information about Discovery tools and flows, visit: www.synopsys.com/products/solutions/discovery_platform.html