Design Flow Augmentation Rapidly integrate advanced new tool features into your flow

At-A-Glance

• Assess current design flow and methodologies and address gaps
• Rapidly integrate new tool capabilities into the flow using production-proven methodologies and reference scripts
• Enhance your design team’s productivity through dedicated assistance and knowledge transfer from specialists
• Maximize your EDA tool investment

Keeping pace with design complexity means keeping design flows up to date with the latest tools and methods. Complex design issues such as low power, designfor- test (DFT) and design-for-yield require design teams to take full advantage of the newest features of their EDA tools if project deliverables are to be completed in a predictable manner. However, this can be easier said than done, since design teams are often simultaneously dealing with project issues while trying to upgrade and optimize their flows.

Design Flow Augmentation services from Synopsys can help ensure your design flow is updated with the latest technologies for nanometer-scale designs. Synopsys consultants continually receive extensive training on the latest tools and design techniques, and have extensive experience deploying them. By leveraging Synopsys tool specialists -- backed by an extensive network of expert resources and support collateral – your critical project milestones can remain on-track while you integrate new design capabilities into your flow.

Figure 1: Synopsys’ Galaxy tools are highly integrated to provide
a complete solution for addressing complex issues such as low
power and test that span multiple phases of the design flow.

Synopsys Design Flow Augmentation services provide experienced consultants that can help you:

• Review, assess, and provide test case results to augment your existing design flows
• Enhance tool sub-flows within your existing environment, particularly for
• Design Compiler®
• IC Compiler™
• JupiterXT™
• PrimeTime® (SI, PX, VX)
• Integrate new tool features throughout the design flow to address specific design goals, such as
• Power optimization
• Multi-Vth, Multi-VDD
• Topographical synthesis for power correlation
• MTCMOS (multi-threshhold CMOS)
• Power-aware placement and verification
• Power-aware ATPG
• SI/Timing closure
• Library-aware synthesis (mapping and structuring)
• Datapath optimization
• Topographical synthesis
• Virtual flat floorplanning, timing and congestion-driven macro placement
• Multi-corner, multi-mode timing optimization
• Variation-aware analysis
• DFT
• Physically-aware scan chain optimization and placement
• Scan-chain partitioning and reordering
• Adaptive Scan Compression
• Small-Delay Defect (SDD) ATPG
• Yield and Reliability
• Lithography compliance checking
• Model-based CMP

Customer Case Study
An industry-leading interconnect chip company was experiencing difficulty closing timing on a critical block of their next-generation cross-bar switch design. In addition to a large gate count with aggressive clock speeds, the nature of the new design led to highly congested, underutilized areas in the center of the chip. Synopsys consultants, working with the customer’s design team, leveraged advanced features of Synopsys’ tools to improve the quality of both the netlist and floorplan. The results were dramatic: not only was timing closure achieved, but the optimizations also delivered a 30% decrease in area, and a 2X improvement in cell utilization, eliminating congestion problems.

Figure 2: Synopsys consultants can recommend tool updates and new
methods that address common design challenges, then help rapidly them
into your flows. This is especially valuable when transitioning to a new
process node or implementing a substantially new design.

For more information about Galaxy tools and tool flows, visit www.synopsys.com/products/solutions/galaxy_platform.html.